1 /* 2 * Copyright (C) 2018-2022 Intel Corporation. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _TPM_H_ 8 #define _TPM_H_ 9 10 #include "mmio_dev.h" 11 #include "acpi.h" 12 13 #define TPM_CRB_MMIO_ADDR 0xFED40000UL 14 #define TPM_CRB_MMIO_SIZE 0x5000U 15 16 uint32_t get_vtpm_crb_mmio_addr(void); 17 uint32_t get_tpm_crb_mmio_addr(void); 18 int basl_fwrite_tpm2(FILE *fp, struct vmctx *ctx); 19 20 struct acpi_table_tpm2 { 21 struct acpi_table_hdr header; 22 uint16_t platform_class; 23 uint16_t reserved; 24 uint64_t control_address; 25 uint32_t start_method; 26 uint8_t start_method_spec_para[12]; 27 uint32_t laml; 28 uint64_t lasa; 29 } __attribute__((packed)); 30 31 /* TPM CRB registers */ 32 enum { 33 CRB_REGS_LOC_STATE = 0x00, 34 CRB_REGS_RESERVED0 = 0x04, 35 CRB_REGS_LOC_CTRL = 0x08, 36 CRB_REGS_LOC_STS = 0x0C, 37 CRB_REGS_RESERVED1 = 0x10, 38 CRB_REGS_INTF_ID_LO = 0x30, 39 CRB_REGS_INTF_ID_HI = 0x34, 40 CRB_REGS_CTRL_EXT_LO = 0x38, 41 CRB_REGS_CTRL_EXT_HI = 0x3C, 42 CRB_REGS_CTRL_REQ = 0x40, 43 CRB_REGS_CTRL_STS = 0x44, 44 CRB_REGS_CTRL_CANCEL = 0x48, 45 CRB_REGS_CTRL_START = 0x4C, 46 CRB_REGS_CTRL_INT_ENABLE = 0x50, 47 CRB_REGS_CTRL_INT_STS = 0x54, 48 CRB_REGS_CTRL_CMD_SIZE = 0x58, 49 CRB_REGS_CTRL_CMD_PA_LO = 0x5C, 50 CRB_REGS_CTRL_CMD_PA_HI = 0x60, 51 CRB_REGS_CTRL_RSP_SIZE = 0x64, 52 CRB_REGS_CTRL_RSP_PA = 0x68, 53 CRB_DATA_BUFFER = 0x80 54 }; 55 56 #define TPM_CRB_REG_SIZE (CRB_DATA_BUFFER) 57 #define TPM_CRB_DATA_BUFFER_SIZE ((TPM_CRB_MMIO_SIZE) - (TPM_CRB_REG_SIZE)) 58 59 /* APIs by tpm.c */ 60 /* Initialize Virtual TPM2 */ 61 void init_vtpm2(struct vmctx *ctx); 62 63 /* Deinitialize Virtual TPM2 */ 64 void deinit_vtpm2(struct vmctx *ctx); 65 66 /* Parse Virtual TPM option from command line */ 67 int acrn_parse_vtpm2(char *arg); 68 69 #endif 70