1 /*
2 * Copyright (C) 2018-2022 Intel Corporation.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <types.h>
8 #include <rtl.h>
9 #include <acrn_common.h>
10 #include <asm/host_pm.h>
11 #include <asm/cpu_caps.h>
12 #include <asm/board.h>
13
14 /* The table includes cpu px info of Intel A3960 SoC */
15 static const struct acrn_pstate_data px_a3960[17] = {
16 {0x960UL, 0UL, 0xAUL, 0xAUL, 0x1800UL, 0x1800UL}, /* P0 */
17 {0x8FCUL, 0UL, 0xAUL, 0xAUL, 0x1700UL, 0x1700UL}, /* P1 */
18 {0x898UL, 0UL, 0xAUL, 0xAUL, 0x1600UL, 0x1600UL}, /* P2 */
19 {0x834UL, 0UL, 0xAUL, 0xAUL, 0x1500UL, 0x1500UL}, /* P3 */
20 {0x7D0UL, 0UL, 0xAUL, 0xAUL, 0x1400UL, 0x1400UL}, /* P4 */
21 {0x76CUL, 0UL, 0xAUL, 0xAUL, 0x1300UL, 0x1300UL}, /* P5 */
22 {0x708UL, 0UL, 0xAUL, 0xAUL, 0x1200UL, 0x1200UL}, /* P6 */
23 {0x6A4UL, 0UL, 0xAUL, 0xAUL, 0x1100UL, 0x1100UL}, /* P7 */
24 {0x640UL, 0UL, 0xAUL, 0xAUL, 0x1000UL, 0x1000UL}, /* P8 */
25 {0x5DCUL, 0UL, 0xAUL, 0xAUL, 0x0F00UL, 0x0F00UL}, /* P9 */
26 {0x578UL, 0UL, 0xAUL, 0xAUL, 0x0E00UL, 0x0E00UL}, /* P10 */
27 {0x514UL, 0UL, 0xAUL, 0xAUL, 0x0D00UL, 0x0D00UL}, /* P11 */
28 {0x4B0UL, 0UL, 0xAUL, 0xAUL, 0x0C00UL, 0x0C00UL}, /* P12 */
29 {0x44CUL, 0UL, 0xAUL, 0xAUL, 0x0B00UL, 0x0B00UL}, /* P13 */
30 {0x3E8UL, 0UL, 0xAUL, 0xAUL, 0x0A00UL, 0x0A00UL}, /* P14 */
31 {0x384UL, 0UL, 0xAUL, 0xAUL, 0x0900UL, 0x0900UL}, /* P15 */
32 {0x320UL, 0UL, 0xAUL, 0xAUL, 0x0800UL, 0x0800UL} /* P16 */
33 };
34
35 /* The table includes cpu cx info of Intel Broxton SoC such as A39x0, J3455, N3350 */
36 static const struct acrn_cstate_data cx_bxt[3] = {
37 {{SPACE_FFixedHW, 0x0U, 0U, 0U, 0UL}, 0x1U, 0x1U, 0x3E8UL}, /* C1 */
38 {{SPACE_SYSTEM_IO, 0x8U, 0U, 0U, 0x415UL}, 0x2U, 0x32U, 0x0AUL}, /* C2 */
39 {{SPACE_SYSTEM_IO, 0x8U, 0U, 0U, 0x419UL}, 0x3U, 0x96U, 0x0AUL} /* C3 */
40 };
41
42 /* The table includes cpu px info of Intel A3950 SoC */
43 static const struct acrn_pstate_data px_a3950[13] = {
44 {0x7D0UL, 0UL, 0xAUL, 0xAUL, 0x1400UL, 0x1400UL}, /* P0 */
45 {0x76CUL, 0UL, 0xAUL, 0xAUL, 0x1300UL, 0x1300UL}, /* P1 */
46 {0x708UL, 0UL, 0xAUL, 0xAUL, 0x1200UL, 0x1200UL}, /* P2 */
47 {0x6A4UL, 0UL, 0xAUL, 0xAUL, 0x1100UL, 0x1100UL}, /* P3 */
48 {0x640UL, 0UL, 0xAUL, 0xAUL, 0x1000UL, 0x1000UL}, /* P4 */
49 {0x5DCUL, 0UL, 0xAUL, 0xAUL, 0x0F00UL, 0x0F00UL}, /* P5 */
50 {0x578UL, 0UL, 0xAUL, 0xAUL, 0x0E00UL, 0x0E00UL}, /* P6 */
51 {0x514UL, 0UL, 0xAUL, 0xAUL, 0x0D00UL, 0x0D00UL}, /* P7 */
52 {0x4B0UL, 0UL, 0xAUL, 0xAUL, 0x0C00UL, 0x0C00UL}, /* P8 */
53 {0x44CUL, 0UL, 0xAUL, 0xAUL, 0x0B00UL, 0x0B00UL}, /* P9 */
54 {0x3E8UL, 0UL, 0xAUL, 0xAUL, 0x0A00UL, 0x0A00UL}, /* P10 */
55 {0x384UL, 0UL, 0xAUL, 0xAUL, 0x0900UL, 0x0900UL}, /* P11 */
56 {0x320UL, 0UL, 0xAUL, 0xAUL, 0x0800UL, 0x0800UL} /* P12 */
57 };
58
59 /* The table includes cpu px info of Intel J3455 SoC */
60 static const struct acrn_pstate_data px_j3455[9] = {
61 {0x5DDUL, 0UL, 0xAUL, 0xAUL, 0x1700UL, 0x1700UL}, /* P0 */
62 {0x5DCUL, 0UL, 0xAUL, 0xAUL, 0x0F00UL, 0x0F00UL}, /* P1 */
63 {0x578UL, 0UL, 0xAUL, 0xAUL, 0x0E00UL, 0x0E00UL}, /* P2 */
64 {0x514UL, 0UL, 0xAUL, 0xAUL, 0x0D00UL, 0x0D00UL}, /* P3 */
65 {0x4B0UL, 0UL, 0xAUL, 0xAUL, 0x0C00UL, 0x0C00UL}, /* P4 */
66 {0x44CUL, 0UL, 0xAUL, 0xAUL, 0x0B00UL, 0x0B00UL}, /* P5 */
67 {0x3E8UL, 0UL, 0xAUL, 0xAUL, 0x0A00UL, 0x0A00UL}, /* P6 */
68 {0x384UL, 0UL, 0xAUL, 0xAUL, 0x0900UL, 0x0900UL}, /* P7 */
69 {0x320UL, 0UL, 0xAUL, 0xAUL, 0x0800UL, 0x0800UL} /* P8 */
70 };
71
72 /* The table includes cpu px info of Intel N3350 SoC */
73 static const struct acrn_pstate_data px_n3350[5] = {
74 {0x44DUL, 0UL, 0xAUL, 0xAUL, 0x1800UL, 0x1800UL}, /* P0 */
75 {0x44CUL, 0UL, 0xAUL, 0xAUL, 0x0B00UL, 0x0B00UL}, /* P1 */
76 {0x3E8UL, 0UL, 0xAUL, 0xAUL, 0x0A00UL, 0x0A00UL}, /* P2 */
77 {0x384UL, 0UL, 0xAUL, 0xAUL, 0x0900UL, 0x0900UL}, /* P3 */
78 {0x320UL, 0UL, 0xAUL, 0xAUL, 0x0800UL, 0x0800UL} /* P4 */
79 };
80
81 /* The table includes cpu cx info of Intel i7-8650U SoC */
82 static const struct acrn_pstate_data px_i78650[16] = {
83 {0x835UL, 0x0UL, 0xAUL, 0xAUL, 0x2A00UL, 0x2A00UL}, /* P0 */
84 {0x834UL, 0x0UL, 0xAUL, 0xAUL, 0x1500UL, 0x1500UL}, /* P1 */
85 {0x76CUL, 0x0UL, 0xAUL, 0xAUL, 0x1300UL, 0x1300UL}, /* P2 */
86 {0x708UL, 0x0UL, 0xAUL, 0xAUL, 0x1200UL, 0x1200UL}, /* P3 */
87 {0x6A4UL, 0x0UL, 0xAUL, 0xAUL, 0x1100UL, 0x1100UL}, /* P4 */
88 {0x640UL, 0x0UL, 0xAUL, 0xAUL, 0x1000UL, 0x1000UL}, /* P5 */
89 {0x5DCUL, 0x0UL, 0xAUL, 0xAUL, 0x0F00UL, 0x0F00UL}, /* P6 */
90 {0x578UL, 0x0UL, 0xAUL, 0xAUL, 0x0E00UL, 0x0E00UL}, /* P7 */
91 {0x4B0UL, 0x0UL, 0xAUL, 0xAUL, 0x0C00UL, 0x0C00UL}, /* P8 */
92 {0x44CUL, 0x0UL, 0xAUL, 0xAUL, 0x0B00UL, 0x0B00UL}, /* P9 */
93 {0x3E8UL, 0x0UL, 0xAUL, 0xAUL, 0x0A00UL, 0x0A00UL}, /* P10 */
94 {0x320UL, 0x0UL, 0xAUL, 0xAUL, 0x0800UL, 0x0800UL}, /* P11 */
95 {0x2BCUL, 0x0UL, 0xAUL, 0xAUL, 0x0700UL, 0x0700UL}, /* P12 */
96 {0x258UL, 0x0UL, 0xAUL, 0xAUL, 0x0600UL, 0x0600UL}, /* P13 */
97 {0x1F4UL, 0x0UL, 0xAUL, 0xAUL, 0x0500UL, 0x0500UL}, /* P14 */
98 {0x190UL, 0x0UL, 0xAUL, 0xAUL, 0x0400UL, 0x0400UL} /* P15 */
99 };
100
101 /* The table includes cpu cx info of Intel i7-8650U SoC */
102 static const struct acrn_cstate_data cx_i78650[3] = {
103 {{SPACE_FFixedHW, 0x0U, 0U, 0U, 0UL}, 0x1U, 0x1U, 0UL}, /* C1 */
104 {{SPACE_SYSTEM_IO, 0x8U, 0U, 0U, 0x1816UL}, 0x2U, 0x97U, 0UL}, /* C2 */
105 {{SPACE_SYSTEM_IO, 0x8U, 0U, 0U, 0x1819UL}, 0x3U, 0x40AU, 0UL} /* C3 */
106 };
107
108 static const struct cpu_state_table cpu_state_tbl[5] = {
109 {"Intel(R) Atom(TM) Processor A3960 @ 1.90GHz",
110 {(uint8_t)ARRAY_SIZE(px_a3960), px_a3960,
111 (uint8_t)ARRAY_SIZE(cx_bxt), cx_bxt}
112 },
113 {"Intel(R) Atom(TM) Processor A3950 @ 1.60GHz",
114 {(uint8_t)ARRAY_SIZE(px_a3950), px_a3950,
115 (uint8_t)ARRAY_SIZE(cx_bxt), cx_bxt}
116 },
117 {"Intel(R) Celeron(R) CPU J3455 @ 1.50GHz",
118 {(uint8_t)ARRAY_SIZE(px_j3455), px_j3455,
119 (uint8_t)ARRAY_SIZE(cx_bxt), cx_bxt}
120 },
121 {"Intel(R) Celeron(R) CPU N3350 @ 1.10GHz",
122 {(uint8_t)ARRAY_SIZE(px_n3350), px_n3350,
123 (uint8_t)ARRAY_SIZE(cx_bxt), cx_bxt}
124 },
125 {"Intel(R) Core(TM) i7-8650U CPU @ 1.90GHz",
126 {(uint8_t)ARRAY_SIZE(px_i78650), px_i78650,
127 (uint8_t)ARRAY_SIZE(cx_i78650), cx_i78650}
128 }
129 };
130
131 static struct cpu_state_info cpu_pm_state_info;
132
get_state_tbl_idx(const char * cpuname)133 static int32_t get_state_tbl_idx(const char *cpuname)
134 {
135 int32_t i;
136 int32_t count = (int32_t)ARRAY_SIZE(cpu_state_tbl);
137 int32_t ret = -1;
138
139 if (cpuname != NULL) {
140 for (i = 0; i < count; i++) {
141 if (strcmp((cpu_state_tbl[i].model_name), cpuname) == 0) {
142 ret = i;
143 break;
144 }
145 }
146 }
147
148 return ret;
149 }
150
get_cpu_pm_state_info(void)151 struct cpu_state_info *get_cpu_pm_state_info(void)
152 {
153 return &cpu_pm_state_info;
154 }
155
load_cpu_state_info(const struct cpu_state_info * state_info)156 static void load_cpu_state_info(const struct cpu_state_info *state_info)
157 {
158 if ((state_info->px_cnt != 0U) && (state_info->px_data != NULL)) {
159 if (state_info->px_cnt > MAX_PSTATE) {
160 cpu_pm_state_info.px_cnt = MAX_PSTATE;
161 } else {
162 cpu_pm_state_info.px_cnt = state_info->px_cnt;
163 }
164
165 cpu_pm_state_info.px_data = state_info->px_data;
166 }
167
168 if ((state_info->cx_cnt != 0U) && (state_info->cx_data != NULL)) {
169 if (state_info->cx_cnt > MAX_CX_ENTRY) {
170 cpu_pm_state_info.cx_cnt = MAX_CX_ENTRY;
171 } else {
172 cpu_pm_state_info.cx_cnt = state_info->cx_cnt;
173 }
174
175 cpu_pm_state_info.cx_data = state_info->cx_data;
176 }
177 }
178
load_pcpu_state_data(void)179 void load_pcpu_state_data(void)
180 {
181 int32_t tbl_idx;
182 const struct cpu_state_info *state_info = NULL;
183 struct cpuinfo_x86 *cpu_info = get_pcpu_info();
184
185 (void)memset(&cpu_pm_state_info, 0U, sizeof(struct cpu_state_info));
186
187 tbl_idx = get_state_tbl_idx(cpu_info->model_name);
188
189 if (tbl_idx >= 0) {
190 /* The cpu state table is found at global cpu_state_tbl[]. */
191 state_info = &(cpu_state_tbl + tbl_idx)->state_info;
192 } else {
193 /* check whether board.c has a valid cpu state table which generated by offline tool */
194 if (strcmp((board_cpu_state_tbl.model_name), cpu_info->model_name) == 0) {
195 state_info = &board_cpu_state_tbl.state_info;
196 }
197 }
198 if (state_info != NULL) {
199 load_cpu_state_info(state_info);
200 }
201 }
202