1 /*
2 * Copyright (C) 2018-2022 Intel Corporation.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <types.h>
8 #include <asm/gdt.h>
9 #include <asm/per_cpu.h>
10
set_tss_desc(struct tss_64_descriptor * desc,uint64_t tss,size_t tss_limit,uint32_t type)11 static void set_tss_desc(struct tss_64_descriptor *desc,
12 uint64_t tss, size_t tss_limit, uint32_t type)
13 {
14 uint32_t u1, u2, u3;
15 uint32_t tss_hi_32 = (uint32_t)(tss >> 32U);
16 uint32_t tss_lo_32 = (uint32_t)tss;
17
18 u1 = tss_lo_32 << 16U;
19 u2 = tss_lo_32 & 0xFF000000U;
20 u3 = (tss_lo_32 & 0x00FF0000U) >> 16U;
21
22
23 desc->low32_value = u1 | (tss_limit & 0xFFFFU);
24 desc->base_addr_63_32 = tss_hi_32;
25 desc->high32_value = u2 | (type << 8U) | 0x8000U | u3;
26 }
27
load_gdt(struct host_gdt_descriptor * gdtr)28 static inline void load_gdt(struct host_gdt_descriptor *gdtr)
29 {
30 asm volatile ("lgdt %0" ::"m"(*gdtr));
31 }
32
load_gdtr_and_tr(void)33 void load_gdtr_and_tr(void)
34 {
35 struct host_gdt *gdt = &get_cpu_var(gdt);
36 struct host_gdt_descriptor gdtr;
37 struct tss_64 *tss = &get_cpu_var(tss);
38
39 /* first entry is not used */
40 gdt->rsvd = 0xAAAAAAAAAAAAAAAAUL;
41 /* ring 0 code sel descriptor */
42 gdt->code_segment_descriptor = 0x00Af9b000000ffffUL;
43 /* ring 0 data sel descriptor */
44 gdt->data_segment_descriptor = 0x00cf93000000ffffUL;
45
46 tss->ist1 = (uint64_t)get_cpu_var(mc_stack) + CONFIG_STACK_SIZE;
47 tss->ist2 = (uint64_t)get_cpu_var(df_stack) + CONFIG_STACK_SIZE;
48 tss->ist3 = (uint64_t)get_cpu_var(sf_stack) + CONFIG_STACK_SIZE;
49 tss->ist4 = 0UL;
50
51 /* tss descriptor */
52 set_tss_desc(&gdt->host_gdt_tss_descriptors,
53 (uint64_t)tss, sizeof(struct tss_64), TSS_AVAIL);
54
55 gdtr.len = sizeof(struct host_gdt) - 1U;
56 gdtr.gdt = gdt;
57
58 load_gdt(&gdtr);
59
60 CPU_LTR_EXECUTE(HOST_GDT_RING0_CPU_TSS_SEL);
61 }
62