1 /*
2 * Copyright (C) 2020-2022 Intel Corporation.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <types.h>
8 #include <asm/cpu.h>
9 #include <asm/cpu_caps.h>
10 #include <asm/cpufeatures.h>
11 #include <asm/cpuid.h>
12 #include <errno.h>
13 #include <logmsg.h>
14 #include <asm/rdt.h>
15 #include <asm/lib/bits.h>
16 #include <asm/board.h>
17 #include <asm/vm_config.h>
18 #include <asm/msr.h>
19
20 const uint16_t hv_clos = 0U;
21 /* RDT features can support different numbers of CLOS. Set the lowest numerical
22 * clos value (common_num_closids - 1) that is common between the resources as
23 * each resource's clos max value to have consistent allocation.
24 */
25 #ifdef CONFIG_RDT_ENABLED
26
27 /*
28 * @pre res == RDT_RESOURCE_L3 || res == RDT_RESOURCE_L2 || res == RDT_RESOURCE_MBA
29 */
get_rdt_res_ins(int res,uint16_t pcpu_id)30 const struct rdt_ins *get_rdt_res_ins(int res, uint16_t pcpu_id)
31 {
32 uint32_t i;
33 struct rdt_type *info = &res_cap_info[res];
34 struct rdt_ins *ins = NULL;
35
36 for (i = 0U; i < info->num_ins; i++) {
37 if (bitmap_test(pcpu_id, &info->ins_array[i].cpu_mask)) {
38 ins = &info->ins_array[i];
39 break;
40 }
41 }
42 return ins;
43 }
44
setup_res_clos_msr(uint16_t pcpu_id,struct rdt_type * info,struct rdt_ins * ins)45 static void setup_res_clos_msr(uint16_t pcpu_id, struct rdt_type *info, struct rdt_ins *ins)
46 {
47 uint16_t i;
48 uint32_t msr_index;
49 uint64_t val = 0;
50 uint32_t res = info->res_id;
51 union clos_config *cfg = ins->clos_config_array;
52
53 if (res != RDT_RESID_MBA && ins->res.cache.is_cdp_enabled) {
54 /* enable CDP before setting COS to simplify CAT mask remapping
55 * and prevent unintended behavior.
56 */
57 msr_write(info->msr_qos_cfg, 0x1UL);
58 }
59
60 for (i = 0U; i < ins->num_clos_config; i++) {
61 switch (res) {
62 case RDT_RESOURCE_L3:
63 case RDT_RESOURCE_L2:
64 val = (uint64_t)cfg[i].clos_mask;
65 break;
66 case RDT_RESOURCE_MBA:
67 val = (uint64_t)cfg[i].mba_delay;
68 break;
69 default:
70 ASSERT(res < RDT_NUM_RESOURCES, "Support only 3 RDT resources. res=%d is invalid", res);
71 }
72 msr_index = info->msr_base + i;
73 msr_write_pcpu(msr_index, val, pcpu_id);
74 }
75 }
76
setup_clos(uint16_t pcpu_id)77 void setup_clos(uint16_t pcpu_id)
78 {
79 uint16_t i, j;
80 struct rdt_type *info;
81 struct rdt_ins *ins;
82
83 for (i = 0U; i < RDT_NUM_RESOURCES; i++) {
84 info = &res_cap_info[i];
85 for (j = 0U; j < info->num_ins; j++) {
86 ins = &info->ins_array[j];
87 if (bitmap_test(pcpu_id, &ins->cpu_mask)) {
88 setup_res_clos_msr(pcpu_id, info, ins);
89 }
90 }
91 }
92
93 /* set hypervisor RDT resource clos */
94 msr_write_pcpu(MSR_IA32_PQR_ASSOC, clos2pqr_msr(hv_clos), pcpu_id);
95 }
96
clos2pqr_msr(uint16_t clos)97 uint64_t clos2pqr_msr(uint16_t clos)
98 {
99 uint64_t pqr_assoc;
100
101 pqr_assoc = msr_read(MSR_IA32_PQR_ASSOC);
102 pqr_assoc = (pqr_assoc & 0xffffffffUL) | ((uint64_t)clos << 32U);
103
104 return pqr_assoc;
105 }
106
is_rdt_type_capable(struct rdt_type * info)107 static bool is_rdt_type_capable(struct rdt_type *info)
108 {
109 uint32_t i;
110 struct rdt_ins *ins;
111 bool ret = false;
112
113 if (info->num_ins > 0U) {
114 for (i = 0U; i < info->num_ins; i++) {
115 ins = &info->ins_array[i];
116 if (ins->num_closids > 0U) {
117 ret = true;
118 break;
119 }
120 }
121 }
122
123 return ret;
124 }
125
is_platform_rdt_capable(void)126 bool is_platform_rdt_capable(void)
127 {
128 bool ret = false;
129
130 if (is_rdt_type_capable(&res_cap_info[RDT_RESOURCE_L3]) ||
131 is_rdt_type_capable(&res_cap_info[RDT_RESOURCE_L2]) ||
132 is_rdt_type_capable(&res_cap_info[RDT_RESOURCE_MBA])) {
133 ret = true;
134 }
135
136 return ret;
137 }
138 #else
clos2pqr_msr(__unused uint16_t clos)139 uint64_t clos2pqr_msr(__unused uint16_t clos)
140 {
141 return 0UL;
142 }
143
is_platform_rdt_capable(void)144 bool is_platform_rdt_capable(void)
145 {
146 return false;
147 }
148 #endif
149