1 /*
2 * Copyright (c) 2011 NetApp, Inc.
3 * Copyright (c) 2018-2022 Intel Corporation.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29 #include <asm/guest/vm.h>
30 #include "vpci_priv.h"
31 #include <asm/guest/ept.h>
32 #include <asm/guest/virq.h>
33 #include <logmsg.h>
34 #include <hash.h>
35
36 /**
37 * @pre vdev != NULL
38 */
pci_vdev_read_vcfg(const struct pci_vdev * vdev,uint32_t offset,uint32_t bytes)39 uint32_t pci_vdev_read_vcfg(const struct pci_vdev *vdev, uint32_t offset, uint32_t bytes)
40 {
41 uint32_t val;
42
43 switch (bytes) {
44 case 1U:
45 val = vdev->cfgdata.data_8[offset];
46 break;
47 case 2U:
48 val = vdev->cfgdata.data_16[offset >> 1U];
49 break;
50 default:
51 val = vdev->cfgdata.data_32[offset >> 2U];
52 break;
53 }
54
55 return val;
56 }
57
58 /**
59 * @pre vdev != NULL
60 */
pci_vdev_write_vcfg(struct pci_vdev * vdev,uint32_t offset,uint32_t bytes,uint32_t val)61 void pci_vdev_write_vcfg(struct pci_vdev *vdev, uint32_t offset, uint32_t bytes, uint32_t val)
62 {
63 switch (bytes) {
64 case 1U:
65 vdev->cfgdata.data_8[offset] = (uint8_t)val;
66 break;
67 case 2U:
68 vdev->cfgdata.data_16[offset >> 1U] = (uint16_t)val;
69 break;
70 default:
71 vdev->cfgdata.data_32[offset >> 2U] = val;
72 break;
73 }
74 }
75
76 /**
77 * @pre vpci != NULL
78 */
pci_find_vdev(struct acrn_vpci * vpci,union pci_bdf vbdf)79 struct pci_vdev *pci_find_vdev(struct acrn_vpci *vpci, union pci_bdf vbdf)
80 {
81 struct pci_vdev *vdev = NULL, *tmp;
82 struct hlist_node *n;
83
84 hlist_for_each(n, &vpci->vdevs_hlist_heads[hash64(vbdf.value, VDEV_LIST_HASHBITS)]) {
85 tmp = hlist_entry(n, struct pci_vdev, link);
86 if (bdf_is_equal(vbdf, tmp->bdf)) {
87 vdev = tmp;
88 break;
89 }
90 }
91
92 return vdev;
93 }
94
is_pci_mem_bar_base_valid(struct acrn_vm * vm,uint64_t base)95 static bool is_pci_mem_bar_base_valid(struct acrn_vm *vm, uint64_t base)
96 {
97 struct acrn_vpci *vpci = &vm->vpci;
98 struct pci_mmio_res *res = (base < (1UL << 32UL)) ? &(vpci->res32): &(vpci->res64);
99
100 return ((base >= res->start) && (base <= res->end));
101 }
102
pci_vdev_update_vbar_base(struct pci_vdev * vdev,uint32_t idx)103 static void pci_vdev_update_vbar_base(struct pci_vdev *vdev, uint32_t idx)
104 {
105 struct pci_vbar *vbar;
106 uint64_t base = 0UL;
107 uint32_t lo, hi, offset;
108 struct pci_mmio_res *res;
109
110 vbar = &vdev->vbars[idx];
111 offset = pci_bar_offset(idx);
112 lo = pci_vdev_read_vcfg(vdev, offset, 4U);
113 if ((!is_pci_reserved_bar(vbar)) && !vbar->sizing) {
114 base = lo & vbar->mask;
115
116 if (is_pci_mem64lo_bar(vbar)) {
117 vbar = &vdev->vbars[idx + 1U];
118 if (!vbar->sizing) {
119 hi = pci_vdev_read_vcfg(vdev, (offset + 4U), 4U);
120 base |= ((uint64_t)hi << 32U);
121 } else {
122 base = 0UL;
123 }
124 }
125
126 if (is_pci_io_bar(vbar)) {
127 /* Because guest driver may write to upper 16-bits of PIO BAR and expect that should have no effect,
128 * SO PIO BAR base may bigger than 0xffff after calculation, should mask the upper 16-bits.
129 */
130 base &= 0xffffUL;
131 }
132 }
133
134 if (base != 0UL) {
135 if (is_pci_io_bar(vbar)) {
136 /*
137 * ACRN-DM and acrn-config should ensure the identical mapping of PIO bar of pass-thru devs.
138 * Currently, we don't support the reprogram of PIO bar of pass-thru devs,
139 * If guest tries to reprogram, hv will inject #GP to guest.
140 */
141 if ((vdev->pdev != NULL) && ((lo & PCI_BASE_ADDRESS_IO_MASK) != (uint32_t)vbar->base_hpa)) {
142 struct acrn_vcpu *vcpu = vcpu_from_pid(vpci2vm(vdev->vpci), get_pcpu_id());
143 if (vcpu != NULL) {
144 vcpu_inject_gp(vcpu, 0U);
145 }
146 pr_err("%s, PCI:%02x:%02x.%x PIO BAR%d couldn't be reprogramed, "
147 "the valid value is 0x%lx, but the actual value is 0x%lx",
148 __func__, vdev->bdf.bits.b, vdev->bdf.bits.d, vdev->bdf.bits.f, idx,
149 vdev->vbars[idx].base_hpa, lo & PCI_BASE_ADDRESS_IO_MASK);
150 base = 0UL;
151 }
152 } else {
153 if ((!is_pci_mem_bar_base_valid(vpci2vm(vdev->vpci), base))
154 || (!mem_aligned_check(base, vdev->vbars[idx].size))) {
155 res = (base < (1UL << 32UL)) ? &(vdev->vpci->res32) : &(vdev->vpci->res64);
156 /* VM tries to reprogram vbar address out of pci mmio bar window, it can be caused by:
157 * 1. For Service VM, <board>.xml is misaligned with the actual native platform,
158 * and we get wrong mmio window.
159 * 2. Malicious operation from VM, it tries to reprogram vbar address out of
160 * pci mmio bar window
161 */
162 pr_err("%s reprogram PCI:%02x:%02x.%x BAR%d to addr:0x%lx,"
163 " which is out of mmio window[0x%lx - 0x%lx] or not aligned with size: 0x%lx",
164 __func__, vdev->bdf.bits.b, vdev->bdf.bits.d, vdev->bdf.bits.f, idx, base,
165 res->start, res->end, vdev->vbars[idx].size);
166 }
167 }
168 }
169
170 vdev->vbars[idx].base_gpa = base;
171 }
172
check_pt_dev_pio_bars(struct pci_vdev * vdev)173 int32_t check_pt_dev_pio_bars(struct pci_vdev *vdev)
174 {
175 int32_t ret = 0;
176 uint32_t idx;
177
178 if (vdev->pdev != NULL) {
179 for (idx = 0U; idx < vdev->nr_bars; idx++) {
180 if ((is_pci_io_bar(&vdev->vbars[idx])) && (vdev->vbars[idx].base_gpa != vdev->vbars[idx].base_hpa)) {
181 ret = -EIO;
182 pr_err("%s, PCI:%02x:%02x.%x PIO BAR%d isn't identical mapping, "
183 "host start addr is 0x%lx, while guest start addr is 0x%lx",
184 __func__, vdev->bdf.bits.b, vdev->bdf.bits.d, vdev->bdf.bits.f, idx,
185 vdev->vbars[idx].base_hpa, vdev->vbars[idx].base_gpa);
186 break;
187 }
188 }
189 }
190
191 return ret;
192 }
193
pci_vdev_write_vbar(struct pci_vdev * vdev,uint32_t idx,uint32_t val)194 void pci_vdev_write_vbar(struct pci_vdev *vdev, uint32_t idx, uint32_t val)
195 {
196 struct pci_vbar *vbar;
197 uint32_t bar, offset;
198 uint32_t update_idx = idx;
199
200 vbar = &vdev->vbars[idx];
201 vbar->sizing = (val == ~0U);
202 bar = val & vbar->mask;
203 if (vbar->is_mem64hi) {
204 update_idx -= 1U;
205 } else {
206 if (is_pci_io_bar(vbar)) {
207 bar |= (vbar->bar_type.bits & (~PCI_BASE_ADDRESS_IO_MASK));
208 } else {
209 bar |= (vbar->bar_type.bits & (~PCI_BASE_ADDRESS_MEM_MASK));
210 }
211 }
212 offset = pci_bar_offset(idx);
213 pci_vdev_write_vcfg(vdev, offset, 4U, bar);
214
215 pci_vdev_update_vbar_base(vdev, update_idx);
216 }
217