1 /* 2 * Copyright (C) 2022 Intel Corporation. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MISC_CFG_H 8 #define MISC_CFG_H 9 10 #define SERVICE_VM_ROOTFS "root=/dev/nvme0n1p2 " 11 #define SERVICE_VM_BOOTARGS_DIFF \ 12 "rw rootwait console=tty0 console=ttyS0 consoleblank=0 no_timer_check quiet loglevel=3 " \ 13 "i915.nuclear_pageflip=1 swiotlb=131072 maxcpus=3 hugepagesz=1G hugepages=4 " 14 #define SERVICE_VM_BOOTARGS_MISC "udmabuf.list_limit=8192 " 15 #define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(3U)) 16 #define SERVICE_VM_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(1U) | AFFINITY_CPU(2U)) 17 #define VM2_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U)) 18 #define VM3_CONFIG_CPU_AFFINITY (AFFINITY_CPU(2U)) 19 #ifdef CONFIG_RDT_ENABLED 20 #define HV_SUPPORTED_MAX_CLOS 0U 21 #define MAX_MBA_CLOS_NUM_ENTRIES 0U 22 #define MAX_CACHE_CLOS_NUM_ENTRIES 0U 23 #endif 24 25 #define VM0_BOOT_ARGS \ 26 "rw rootwait root=/dev/sda2 console=tty0 console=ttyS0 consoleblank=0 no_timer_check quiet loglevel=3 " \ 27 "i915.nuclear_pageflip=1 swiotlb=131072 " 28 #define PRE_RTVM_SW_SRAM_MAX_SIZE 0UL 29 30 #endif /* MISC_CFG_H */ 31