1 /*
2  * Copyright (C) 2022 Intel Corporation.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef MISC_CFG_H
8 #define MISC_CFG_H
9 
10 #define VM0_CONFIG_CPU_AFFINITY (AFFINITY_CPU(0U) | AFFINITY_CPU(2U))
11 #define VM1_CONFIG_CPU_AFFINITY (AFFINITY_CPU(1U) | AFFINITY_CPU(3U))
12 #ifdef CONFIG_RDT_ENABLED
13 #define HV_SUPPORTED_MAX_CLOS 0U
14 #define MAX_MBA_CLOS_NUM_ENTRIES 0U
15 #define MAX_CACHE_CLOS_NUM_ENTRIES 0U
16 #endif
17 #define VM0_CONFIG_PCI_DEV_NUM 3U
18 #define VM1_CONFIG_PCI_DEV_NUM 2U
19 
20 #define VM0_BOOT_ARGS                                                                                                  \
21 	"rw rootwait root=/dev/sda2 console=tty0 console=ttyS0 noxsave nohpet no_timer_check ignore_loglevel "         \
22 	"log_buf_len=16M consoleblank=0 tsc=reliable reboot=acpi "
23 #define VM1_BOOT_ARGS                                                                                                  \
24 	"rw rootwait root=/dev/sda2 console=tty0 console=ttyS0 noxsave nohpet no_timer_check ignore_loglevel "         \
25 	"log_buf_len=16M consoleblank=0 tsc=reliable reboot=acpi "
26 #define PRE_RTVM_SW_SRAM_MAX_SIZE 0UL
27 
28 #endif /* MISC_CFG_H */
29