# © 2021 Qualcomm Innovation Center, Inc. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause

base_arch armv8-64

configs ARCH_AARCH64_32BIT_EL0=1
configs ARCH_AARCH64_32BIT_EL0_ALL_CORES=1
configs ARCH_AARCH64_32BIT_EL1=0

# Checked for Cortex-(A55,A65,A75,A76,A77,A78,X1)
configs CPU_HAS_NO_ACTLR_EL1=1
configs CPU_HAS_NO_AMAIR_EL1=1
configs CPU_HAS_NO_AFSR0_EL1=1
configs CPU_HAS_NO_AFSR1_EL1=1

# Mandatory architecture extensions in v8.2
configs ARCH_ARM_FEAT_CSV2=1
configs ARCH_ARM_FEAT_CSV3=1

configs ARCH_ARM_FEAT_HPDS=1
configs ARCH_ARM_FEAT_LSE=1
configs ARCH_ARM_FEAT_LOR=1
configs ARCH_ARM_FEAT_PAN=1
configs ARCH_ARM_FEAT_RDM=1
configs ARCH_ARM_FEAT_VHE=1
configs ARCH_ARM_FEAT_CRC32=1

configs ARCH_ARM_FEAT_ASMv8p2=1
configs ARCH_ARM_FEAT_PAN2=1
configs ARCH_ARM_FEAT_DPB=1
configs ARCH_ARM_FEAT_DEBUGv8p2=1
configs ARCH_ARM_FEAT_DotProd=1
configs ARCH_ARM_FEAT_RAS=1
configs ARCH_ARM_FEAT_TTCNP=1
configs ARCH_ARM_FEAT_XNX=1
configs ARCH_ARM_FEAT_UAO=1

configs ARCH_AARCH64_ASID16=1 ARCH_ARM_PMU_VER=3

# The number of implemented ICH_LR<n>_EL2 registers.
configs CPU_GICH_LR_COUNT=4U

# The number of implemented ICH_APR[01]R<n>_EL2 registers.
configs CPU_GICH_APR_COUNT=1U

# The number of implemented DBGB[CV]R_EL1 (HW breakpoint) registers.
configs CPU_DEBUG_BP_COUNT=6U

# The number of implemented DBGW[CV]R_EL1 (HW watchpoint) registers.
configs CPU_DEBUG_WP_COUNT=4U

# The level of support for ARMv8.4-TTRem on this CPU (encoded the same way
# as ID_AA64MMFR2_EL1.BBM).
configs CPU_PGTABLE_BBM_LEVEL=0U

# These CPUs always have an ETM.
configs PLATFORM_HAS_NO_ETM_BASE=0