1 // © 2021 Qualcomm Innovation Center, Inc. All rights reserved. 2 // 3 // SPDX-License-Identifier: BSD-3-Clause 4 5 // More concise aliases for common atomic operations. 6 7 #include <asm/atomic.h> 8 9 // Shortcuts for load-relaxed and load-acquire 10 #define atomic_load_relaxed(p) atomic_load_explicit((p), memory_order_relaxed) 11 #define atomic_load_acquire(p) atomic_load_explicit((p), memory_order_acquire) 12 13 // Atomic load-consume. 14 // 15 // Perform a load-consume, with the semantics it should have rather than the 16 // semantics it is defined to have in the standard. On most CPUs, this is just 17 // a relaxed atomic load (assuming that volatile has the new semantics specified 18 // in C18, as it does in virtually every C implementation ever). 19 #if !defined(atomic_load_consume) 20 #define atomic_load_consume(p) atomic_load_explicit(p, memory_order_relaxed) 21 #endif 22 23 // Shortcuts for store-relaxed and store-release 24 #define atomic_store_relaxed(p, v) \ 25 atomic_store_explicit((p), (v), memory_order_relaxed) 26 #define atomic_store_release(p, v) \ 27 atomic_store_explicit((p), (v), memory_order_release) 28 29 // Device memory fences 30 // 31 // A fence affecting device accesses may need to use a stronger barrier 32 // instruction compared to a fence affecting only CPU threads. This macro 33 // may be redefined by <asm/atomic.h> to use stronger instructions if necessary. 34 #if !defined(atomic_device_fence) 35 #define atomic_device_fence(o) atomic_thread_fence(o) 36 #endif 37