1 // © 2021 Qualcomm Innovation Center, Inc. All rights reserved. 2 // 3 // SPDX-License-Identifier: BSD-3-Clause 4 5 // Prefetch operations. 6 // 7 // Calling these macros may cause the compiler to generate hint instructions 8 // or otherwise reorder operations so that values are fetched by the CPU 9 // eagerly when it is known that they will be needed in the near future. 10 // 11 // Prefetch instructions, where available, can typically distinguish between 12 // addresses that will be loaded or stored; this distinction is useful on 13 // cache-coherent multiprocessor systems, where a store prefetch will try to 14 // bring the target cache line into an exclusive state. 15 // 16 // On some architectures, including ARMv8, the prefetch instructions can 17 // further distinguish between temporal and non-temporal accesses. A temporal, 18 // or "keep", prefetch means that the address will be accessed repeatedly and 19 // should be kept in the cache (i.e. the default behaviour of most caches). A 20 // non-temporal, or "stream", prefetch means that the address will be accessed 21 // only once, so cache allocations for it should be kept to a minimum - e.g. 22 // bypassing outer caches on eviction from the innermost cache. 23 // 24 // This is in an asm header to allow the macros to be replaced with asm 25 // directives or no-ops for targets where the compiler makes a suboptimal 26 // decision by default, typically because the target CPU has a broken 27 // implementation of the prefetch instructions. 28 29 #ifndef prefetch_load_keep 30 #define prefetch_load_keep(addr) __builtin_prefetch(addr, 0, 3) 31 #endif 32 33 #ifndef prefetch_store_keep 34 #define prefetch_store_keep(addr) __builtin_prefetch(addr, 1, 3) 35 #endif 36 37 #ifndef prefetch_load_stream 38 #define prefetch_load_stream(addr) __builtin_prefetch(addr, 0, 0) 39 #endif 40 41 #ifndef prefetch_store_stream 42 #define prefetch_store_stream(addr) __builtin_prefetch(addr, 1, 0) 43 #endif 44