1# © 2021 Qualcomm Innovation Center, Inc. All rights reserved. 2# 3# SPDX-License-Identifier: BSD-3-Clause 4 5base_arch armv8-64 6 7configs ARCH_AARCH64_32BIT_EL0=1 8configs ARCH_AARCH64_32BIT_EL0_ALL_CORES=1 9configs ARCH_AARCH64_32BIT_EL1=0 10 11# Checked for Cortex-(A55,A65,A75,A76,A77,A78,X1) 12configs CPU_HAS_NO_ACTLR_EL1=1 13configs CPU_HAS_NO_AMAIR_EL1=1 14configs CPU_HAS_NO_AFSR0_EL1=1 15configs CPU_HAS_NO_AFSR1_EL1=1 16 17# Mandatory architecture extensions in v8.2 18configs ARCH_ARM_FEAT_CSV2=1 19configs ARCH_ARM_FEAT_CSV3=1 20 21configs ARCH_ARM_FEAT_HPDS=1 22configs ARCH_ARM_FEAT_LSE=1 23configs ARCH_ARM_FEAT_LOR=1 24configs ARCH_ARM_FEAT_PAN=1 25configs ARCH_ARM_FEAT_RDM=1 26configs ARCH_ARM_FEAT_VHE=1 27configs ARCH_ARM_FEAT_CRC32=1 28 29configs ARCH_ARM_FEAT_ASMv8p2=1 30configs ARCH_ARM_FEAT_PAN2=1 31configs ARCH_ARM_FEAT_DPB=1 32configs ARCH_ARM_FEAT_DEBUGv8p2=1 33configs ARCH_ARM_FEAT_DotProd=1 34configs ARCH_ARM_FEAT_RAS=1 35configs ARCH_ARM_FEAT_TTCNP=1 36configs ARCH_ARM_FEAT_XNX=1 37configs ARCH_ARM_FEAT_UAO=1 38 39configs ARCH_AARCH64_ASID16=1 ARCH_ARM_PMU_VER=3 40 41# The number of implemented ICH_LR<n>_EL2 registers. 42configs CPU_GICH_LR_COUNT=4U 43 44# The number of implemented ICH_APR[01]R<n>_EL2 registers. 45configs CPU_GICH_APR_COUNT=1U 46 47# The number of implemented DBGB[CV]R_EL1 (HW breakpoint) registers. 48configs CPU_DEBUG_BP_COUNT=6U 49 50# The number of implemented DBGW[CV]R_EL1 (HW watchpoint) registers. 51configs CPU_DEBUG_WP_COUNT=4U 52 53# The level of support for ARMv8.4-TTRem on this CPU (encoded the same way 54# as ID_AA64MMFR2_EL1.BBM). 55configs CPU_PGTABLE_BBM_LEVEL=0U 56 57# These CPUs always have an ETM. 58configs PLATFORM_HAS_NO_ETM_BASE=0 59