1 // © 2021 Qualcomm Innovation Center, Inc. All rights reserved.
2 //
3 // SPDX-License-Identifier: BSD-3-Clause
4 
5 // Device memory fences
6 //
7 // The atomic_thread_fence() builtin only generates a fence for CPU threads,
8 // which means the compiler is allowed to use a DMB ISH instruction. For device
9 // accesses this is not good enough; we need a DMB SY.
10 //
11 // Note that the instructions here are the same for AArch64 and ARMv8 AArch32.
12 #define atomic_device_fence(p)                                                 \
13 	do {                                                                   \
14 		switch (p) {                                                   \
15 		case memory_order_relaxed:                                     \
16 			atomic_thread_fence(memory_order_relaxed);             \
17 			break;                                                 \
18 		case memory_order_acquire:                                     \
19 		case memory_order_consume:                                     \
20 			__asm__ volatile("dmb ld" ::: "memory");               \
21 			break;                                                 \
22 		case memory_order_release:                                     \
23 		case memory_order_acq_rel:                                     \
24 		case memory_order_seq_cst:                                     \
25 		default:                                                       \
26 			__asm__ volatile("dmb sy" ::: "memory");               \
27 			break;                                                 \
28 		}                                                              \
29 	} while (0)
30