1 // © 2021 Qualcomm Innovation Center, Inc. All rights reserved.
2 //
3 // SPDX-License-Identifier: BSD-3-Clause
4 
5 // Miscellaneous definitions describing the CPU implementation.
6 
7 // The size in address bits of a line in the innermost visible data cache.
8 #define CPU_L1D_LINE_BITS 6U
9 
10 // The size in address bits of the CPU's DC ZVA block. This is nearly always
11 // the same as CPU_L1D_LINE_BITS.
12 #define CPU_DCZVA_BITS 9U
13 
14 // The largest difference between the source and destination pointers during
15 // the optimised memcpy() for this CPU. This is here because it might depend
16 // on CPU_L1D_LINE_BITS in some implementations.
17 #define CPU_MEMCPY_STRIDE 256U
18