Lines Matching refs:C
77 #define C(_x) PERF_COUNT_HW_CACHE_##_x macro
80 static const unsigned int arc_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
81 [C(L1D)] = {
82 [C(OP_READ)] = {
83 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
84 [C(RESULT_MISS)] = PERF_COUNT_ARC_DCLM,
86 [C(OP_WRITE)] = {
87 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_STC,
88 [C(RESULT_MISS)] = PERF_COUNT_ARC_DCSM,
90 [C(OP_PREFETCH)] = {
91 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
92 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
95 [C(L1I)] = {
96 [C(OP_READ)] = {
97 [C(RESULT_ACCESS)] = PERF_COUNT_HW_INSTRUCTIONS,
98 [C(RESULT_MISS)] = PERF_COUNT_ARC_ICM,
100 [C(OP_WRITE)] = {
101 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
102 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
104 [C(OP_PREFETCH)] = {
105 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
106 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
109 [C(LL)] = {
110 [C(OP_READ)] = {
111 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
112 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
114 [C(OP_WRITE)] = {
115 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
116 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
118 [C(OP_PREFETCH)] = {
119 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
120 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
123 [C(DTLB)] = {
124 [C(OP_READ)] = {
125 [C(RESULT_ACCESS)] = PERF_COUNT_ARC_LDC,
126 [C(RESULT_MISS)] = PERF_COUNT_ARC_EDTLB,
129 [C(OP_WRITE)] = {
130 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
131 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
133 [C(OP_PREFETCH)] = {
134 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
135 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
138 [C(ITLB)] = {
139 [C(OP_READ)] = {
140 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
141 [C(RESULT_MISS)] = PERF_COUNT_ARC_EITLB,
143 [C(OP_WRITE)] = {
144 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
145 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
147 [C(OP_PREFETCH)] = {
148 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
149 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
152 [C(BPU)] = {
153 [C(OP_READ)] = {
154 [C(RESULT_ACCESS)] = PERF_COUNT_HW_BRANCH_INSTRUCTIONS,
155 [C(RESULT_MISS)] = PERF_COUNT_HW_BRANCH_MISSES,
157 [C(OP_WRITE)] = {
158 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
159 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
161 [C(OP_PREFETCH)] = {
162 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
163 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
166 [C(NODE)] = {
167 [C(OP_READ)] = {
168 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
169 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
171 [C(OP_WRITE)] = {
172 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
173 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
175 [C(OP_PREFETCH)] = {
176 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
177 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,