Lines Matching refs:operations
568 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
579 erratum. For very specific sequences of memory operations, it is
611 between two write operations may not ensure the correct visibility
646 corrects this value, ensuring cache maintenance operations which use
650 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
655 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
765 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
872 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
876 operations that do not specify an address execute, relative to
1090 management operations described in ARM document number ARM DEN
1334 such copy operations with large buffers.
1684 Note that gcc does not generate 80-bit operations by default,