Lines Matching refs:D
80 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
83 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
134 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
161 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
200 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
221 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
247 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
249 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
250 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
269 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
286 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
322 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
343 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
351 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
360 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
375 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
396 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
397 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
410 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
413 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4