Lines Matching refs:reset_val
2345 EL2_REG_FILTERED(name, bad_vncr_trap, reset_val, 0, vis)
2845 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
2846 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
2864 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1,
2877 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 },
3026 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
3028 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
3029 { SYS_DESC(SYS_SCTLR2_EL1), access_vm_reg, reset_val, SCTLR2_EL1, 0,
3035 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
3041 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
3042 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0,
3114 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 },
3115 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
3143 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
3150 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
3165 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility },
3166 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility },
3205 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
3372 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },
3376 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1),
3377 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0),
3378 EL2_REG_FILTERED(SCTLR2_EL2, access_vm_reg, reset_val, 0,
3382 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1),
3383 EL2_REG_VNCR(HSTR_EL2, reset_val, 0),
3386 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0),
3387 EL2_REG_VNCR(HACR_EL2, reset_val, 0),
3389 EL2_REG_FILTERED(ZCR_EL2, access_zcr_el2, reset_val, 0,
3392 EL2_REG_VNCR(HCRX_EL2, reset_val, 0),
3394 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0),
3395 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0),
3396 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),
3397 EL2_REG_FILTERED(TCR2_EL2, access_rw, reset_val, TCR2_EL2_RES1,
3399 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0),
3400 EL2_REG_VNCR(VTCR_EL2, reset_val, 0),
3401 EL2_REG_FILTERED(VNCR_EL2, bad_vncr_trap, reset_val, 0,
3413 EL2_REG_REDIR(SPSR_EL2, reset_val, 0),
3414 EL2_REG_REDIR(ELR_EL2, reset_val, 0),
3424 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0),
3425 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0),
3426 EL2_REG_REDIR(ESR_EL2, reset_val, 0),
3428 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 },
3430 EL2_REG_REDIR(FAR_EL2, reset_val, 0),
3431 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0),
3433 EL2_REG(MAIR_EL2, access_rw, reset_val, 0),
3434 EL2_REG_FILTERED(PIRE0_EL2, access_rw, reset_val, 0,
3436 EL2_REG_FILTERED(PIR_EL2, access_rw, reset_val, 0,
3438 EL2_REG_FILTERED(POR_EL2, access_rw, reset_val, 0,
3440 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0),
3453 EL2_REG(VBAR_EL2, access_rw, reset_val, 0),
3493 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0),
3494 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0),
3496 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0),
3497 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0),
3499 EL2_REG(CNTHP_CTL_EL2, access_arch_timer, reset_val, 0),
3500 EL2_REG(CNTHP_CVAL_EL2, access_arch_timer, reset_val, 0),
3503 EL2_REG(CNTHV_CTL_EL2, access_hv_timer, reset_val, 0),
3504 EL2_REG(CNTHV_CVAL_EL2, access_hv_timer, reset_val, 0),