Lines Matching refs:C
727 #define C(_x) PERF_COUNT_HW_CACHE_##_x macro
729 static const int csky_pmu_cache_map[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
730 [C(L1D)] = {
732 [C(OP_READ)] = {
733 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
734 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
736 [C(OP_WRITE)] = {
737 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
738 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
740 [C(OP_PREFETCH)] = {
741 [C(RESULT_ACCESS)] = 0x5,
742 [C(RESULT_MISS)] = 0x6,
745 [C(OP_READ)] = {
746 [C(RESULT_ACCESS)] = 0x14,
747 [C(RESULT_MISS)] = 0x15,
749 [C(OP_WRITE)] = {
750 [C(RESULT_ACCESS)] = 0x16,
751 [C(RESULT_MISS)] = 0x17,
753 [C(OP_PREFETCH)] = {
754 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
755 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
759 [C(L1I)] = {
760 [C(OP_READ)] = {
761 [C(RESULT_ACCESS)] = 0x3,
762 [C(RESULT_MISS)] = 0x4,
764 [C(OP_WRITE)] = {
765 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
766 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
768 [C(OP_PREFETCH)] = {
769 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
770 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
773 [C(LL)] = {
775 [C(OP_READ)] = {
776 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
777 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
779 [C(OP_WRITE)] = {
780 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
781 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
783 [C(OP_PREFETCH)] = {
784 [C(RESULT_ACCESS)] = 0x7,
785 [C(RESULT_MISS)] = 0x8,
788 [C(OP_READ)] = {
789 [C(RESULT_ACCESS)] = 0x18,
790 [C(RESULT_MISS)] = 0x19,
792 [C(OP_WRITE)] = {
793 [C(RESULT_ACCESS)] = 0x1a,
794 [C(RESULT_MISS)] = 0x1b,
796 [C(OP_PREFETCH)] = {
797 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
798 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
802 [C(DTLB)] = {
804 [C(OP_READ)] = {
805 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
806 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
808 [C(OP_WRITE)] = {
809 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
810 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
813 [C(OP_READ)] = {
814 [C(RESULT_ACCESS)] = 0x14,
815 [C(RESULT_MISS)] = 0xb,
817 [C(OP_WRITE)] = {
818 [C(RESULT_ACCESS)] = 0x16,
819 [C(RESULT_MISS)] = 0xb,
822 [C(OP_PREFETCH)] = {
823 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
824 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
827 [C(ITLB)] = {
829 [C(OP_READ)] = {
830 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
831 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
834 [C(OP_READ)] = {
835 [C(RESULT_ACCESS)] = 0x3,
836 [C(RESULT_MISS)] = 0xa,
839 [C(OP_WRITE)] = {
840 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
841 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
843 [C(OP_PREFETCH)] = {
844 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
845 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
848 [C(BPU)] = {
849 [C(OP_READ)] = {
850 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
851 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
853 [C(OP_WRITE)] = {
854 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
855 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
857 [C(OP_PREFETCH)] = {
858 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
859 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
862 [C(NODE)] = {
863 [C(OP_READ)] = {
864 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
865 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
867 [C(OP_WRITE)] = {
868 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
869 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
871 [C(OP_PREFETCH)] = {
872 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
873 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,