Lines Matching refs:div
71 unsigned int mult, unsigned int div) in ath79_set_ff_clk() argument
76 clk = clk_register_fixed_factor(NULL, name, parent, 0, mult, div); in ath79_set_ff_clk()
101 u32 div; in ar71xx_clocks_init() local
107 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; in ar71xx_clocks_init()
108 freq = div * ref_rate; in ar71xx_clocks_init()
110 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; in ar71xx_clocks_init()
111 cpu_rate = freq / div; in ar71xx_clocks_init()
113 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; in ar71xx_clocks_init()
114 ddr_rate = freq / div; in ar71xx_clocks_init()
116 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; in ar71xx_clocks_init()
117 ahb_rate = cpu_rate / div; in ar71xx_clocks_init()
126 u32 mult, div, ddr_div, ahb_div; in ar724x_clocks_init() local
134 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2; in ar724x_clocks_init()
139 ath79_set_ff_clk(ATH79_CLK_CPU, "ref", mult, div); in ar724x_clocks_init()
140 ath79_set_ff_clk(ATH79_CLK_DDR, "ref", mult, div * ddr_div); in ar724x_clocks_init()
141 ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div); in ar724x_clocks_init()