Lines Matching refs:T
65 T = 0, enumerator
939 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
940 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
941 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
948 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
949 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
950 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
999 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },
1000 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
1001 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
1017 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
1018 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1021 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
1022 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1027 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
1028 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
1031 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
1032 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
1035 [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T },
1054 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
1055 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
1058 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
1059 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
1064 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
1065 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
1068 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
1069 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
1075 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
1076 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1079 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
1080 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1098 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
1099 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
1102 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
1103 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
1108 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
1109 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
1112 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
1113 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
1116 [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T },
1140 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1141 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1144 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1145 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1151 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1152 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1155 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1156 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1384 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1385 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1388 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1389 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1394 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1395 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1398 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1399 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1402 [C(RESULT_ACCESS)] = { 23, CNTR_EVEN, T },
1422 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1425 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1737 raw_event.range = T; in mipsxx_pmu_map_raw_event()
1793 raw_event.range = T; in mipsxx_pmu_map_raw_event()
1808 raw_event.range = T; in mipsxx_pmu_map_raw_event()