Lines Matching refs:opcode
530 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) in simulate_ll() argument
541 offset = opcode & OFFSET; in simulate_ll()
546 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); in simulate_ll()
564 regs->regs[(opcode & RT) >> 16] = value; in simulate_ll()
569 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) in simulate_sc() argument
581 offset = opcode & OFFSET; in simulate_sc()
586 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); in simulate_sc()
587 reg = (opcode & RT) >> 16; in simulate_sc()
617 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) in simulate_llsc() argument
619 if ((opcode & OPCODE) == LL) { in simulate_llsc()
622 return simulate_ll(regs, opcode); in simulate_llsc()
624 if ((opcode & OPCODE) == SC) { in simulate_llsc()
627 return simulate_sc(regs, opcode); in simulate_llsc()
672 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) in simulate_rdhwr_normal() argument
674 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { in simulate_rdhwr_normal()
675 int rd = (opcode & RD) >> 11; in simulate_rdhwr_normal()
676 int rt = (opcode & RT) >> 16; in simulate_rdhwr_normal()
686 static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned int opcode) in simulate_rdhwr_mm() argument
688 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { in simulate_rdhwr_mm()
689 int rd = (opcode & MM_RS) >> 16; in simulate_rdhwr_mm()
690 int rt = (opcode & MM_RT) >> 21; in simulate_rdhwr_mm()
699 static int simulate_sync(struct pt_regs *regs, unsigned int opcode) in simulate_sync() argument
701 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { in simulate_sync()
724 unsigned int opcode) in simulate_loongson3_cpucfg() argument
726 int op = opcode & OPCODE; in simulate_loongson3_cpucfg()
727 int op2 = opcode & CSR_OPCODE2_MASK; in simulate_loongson3_cpucfg()
728 int csr_func = (opcode & CSR_FUNC_MASK) >> 16; in simulate_loongson3_cpucfg()
731 int rd = (opcode & RD) >> 11; in simulate_loongson3_cpucfg()
732 int rs = (opcode & RS) >> 21; in simulate_loongson3_cpucfg()
824 static int simulate_fp(struct pt_regs *regs, unsigned int opcode, in simulate_fp() argument
827 union mips_instruction inst = { .word = opcode }; in simulate_fp()
833 switch (inst.i_format.opcode) { in simulate_fp()
961 static int simulate_fp(struct pt_regs *regs, unsigned int opcode, in simulate_fp() argument
1032 unsigned int opcode, bcode; in do_bp() local
1054 opcode = (instr[0] << 16) | instr[1]; in do_bp()
1055 bcode = (opcode >> 6) & ((1 << 20) - 1); in do_bp()
1058 if (__get_inst32(&opcode, (u32 *)epc, user)) in do_bp()
1060 bcode = (opcode >> 6) & ((1 << 20) - 1); in do_bp()
1118 u32 opcode, tcode = 0; in do_tr() local
1130 opcode = (instr[0] << 16) | instr[1]; in do_tr()
1132 if (!(opcode & OPCODE)) in do_tr()
1133 tcode = (opcode >> 12) & ((1 << 4) - 1); in do_tr()
1135 if (__get_inst32(&opcode, (u32 *)epc, user)) in do_tr()
1138 if (!(opcode & OPCODE)) in do_tr()
1139 tcode = (opcode >> 6) & ((1 << 10) - 1); in do_tr()
1159 unsigned int opcode = 0; in do_ri() local
1168 likely(get_user(opcode, epc) >= 0)) { in do_ri()
1171 status = mipsr2_decoder(regs, opcode, &fcr31); in do_ri()
1201 if (unlikely(get_user(opcode, epc) < 0)) in do_ri()
1205 status = simulate_llsc(regs, opcode); in do_ri()
1208 status = simulate_rdhwr_normal(regs, opcode); in do_ri()
1211 status = simulate_sync(regs, opcode); in do_ri()
1214 status = simulate_fp(regs, opcode, old_epc, old31); in do_ri()
1218 status = simulate_loongson3_cpucfg(regs, opcode); in do_ri()
1227 opcode = mmop[0]; in do_ri()
1228 opcode = (opcode << 16) | mmop[1]; in do_ri()
1231 status = simulate_rdhwr_mm(regs, opcode); in do_ri()
1409 unsigned int opcode; in do_cpu() local
1424 opcode = 0; in do_cpu()
1431 if (unlikely(get_user(opcode, epc) < 0)) in do_cpu()
1435 status = simulate_llsc(regs, opcode); in do_cpu()