Lines Matching refs:stat
281 unsigned long stat, mask; in spu_irq_class_0() local
287 stat = spu_int_stat_get(spu, 0) & mask; in spu_irq_class_0()
289 spu->class_0_pending |= stat; in spu_irq_class_0()
295 spu_int_stat_clear(spu, 0, stat); in spu_irq_class_0()
305 unsigned long stat, mask, dar, dsisr; in spu_irq_class_1() local
312 stat = spu_int_stat_get(spu, 1) & mask; in spu_irq_class_1()
315 if (stat & CLASS1_STORAGE_FAULT_INTR) in spu_irq_class_1()
317 spu_int_stat_clear(spu, 1, stat); in spu_irq_class_1()
319 pr_debug("%s: %lx %lx %lx %lx\n", __func__, mask, stat, in spu_irq_class_1()
322 if (stat & CLASS1_SEGMENT_FAULT_INTR) in spu_irq_class_1()
325 if (stat & CLASS1_STORAGE_FAULT_INTR) in spu_irq_class_1()
333 return stat ? IRQ_HANDLED : IRQ_NONE; in spu_irq_class_1()
340 unsigned long stat; in spu_irq_class_2() local
347 stat = spu_int_stat_get(spu, 2); in spu_irq_class_2()
350 stat &= mask; in spu_irq_class_2()
353 if (stat & mailbox_intrs) in spu_irq_class_2()
354 spu_int_mask_and(spu, 2, ~(stat & mailbox_intrs)); in spu_irq_class_2()
356 spu_int_stat_clear(spu, 2, stat); in spu_irq_class_2()
358 pr_debug("class 2 interrupt %d, %lx, %lx\n", irq, stat, mask); in spu_irq_class_2()
360 if (stat & CLASS2_MAILBOX_INTR) in spu_irq_class_2()
363 if (stat & CLASS2_SPU_STOP_INTR) in spu_irq_class_2()
366 if (stat & CLASS2_SPU_HALT_INTR) in spu_irq_class_2()
369 if (stat & CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR) in spu_irq_class_2()
372 if (stat & CLASS2_MAILBOX_THRESHOLD_INTR) in spu_irq_class_2()
379 return stat ? IRQ_HANDLED : IRQ_NONE; in spu_irq_class_2()
658 static DEVICE_ATTR(stat, 0444, spu_stat_show, NULL);