Lines Matching refs:__ASM_SIZE
60 asm_inline volatile(LOCK_PREFIX __ASM_SIZE(bts) " %1,%0" in arch_set_bit()
68 asm volatile(__ASM_SIZE(bts) " %1,%0" : : ADDR, "Ir" (nr) : "memory"); in arch___set_bit()
79 asm_inline volatile(LOCK_PREFIX __ASM_SIZE(btr) " %1,%0" in arch_clear_bit()
94 asm volatile(__ASM_SIZE(btr) " %1,%0" : : ADDR, "Ir" (nr) : "memory"); in arch___clear_bit()
118 asm volatile(__ASM_SIZE(btc) " %1,%0" : : ADDR, "Ir" (nr) : "memory"); in arch___change_bit()
129 asm_inline volatile(LOCK_PREFIX __ASM_SIZE(btc) " %1,%0" in arch_change_bit()
137 return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(bts), *addr, c, "Ir", nr); in arch_test_and_set_bit()
151 asm(__ASM_SIZE(bts) " %2,%1" in arch___test_and_set_bit()
161 return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btr), *addr, c, "Ir", nr); in arch_test_and_clear_bit()
177 asm volatile(__ASM_SIZE(btr) " %2,%1" in arch___test_and_clear_bit()
189 asm volatile(__ASM_SIZE(btc) " %2,%1" in arch___test_and_change_bit()
200 return GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btc), *addr, c, "Ir", nr); in arch_test_and_change_bit()
227 asm volatile(__ASM_SIZE(bt) " %2,%1" in variable_test_bit()