Lines Matching refs:val
141 u64 val; in cmci_set_threshold() local
144 rdmsrq(MSR_IA32_MCx_CTL2(bank), val); in cmci_set_threshold()
145 val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK; in cmci_set_threshold()
146 wrmsrq(MSR_IA32_MCx_CTL2(bank), val | thresh); in cmci_set_threshold()
176 static bool cmci_skip_bank(int bank, u64 *val) in cmci_skip_bank() argument
187 rdmsrq(MSR_IA32_MCx_CTL2(bank), *val); in cmci_skip_bank()
190 if (*val & MCI_CTL2_CMCI_EN) { in cmci_skip_bank()
206 static u64 cmci_pick_threshold(u64 val, int *bios_zero_thresh) in cmci_pick_threshold() argument
208 if ((val & MCI_CTL2_CMCI_THRESHOLD_MASK) == CMCI_STORM_THRESHOLD) in cmci_pick_threshold()
209 return val; in cmci_pick_threshold()
212 val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK; in cmci_pick_threshold()
213 val |= CMCI_THRESHOLD; in cmci_pick_threshold()
214 } else if (!(val & MCI_CTL2_CMCI_THRESHOLD_MASK)) { in cmci_pick_threshold()
221 val |= CMCI_THRESHOLD; in cmci_pick_threshold()
224 return val; in cmci_pick_threshold()
230 static void cmci_claim_bank(int bank, u64 val, int bios_zero_thresh, int *bios_wrong_thresh) in cmci_claim_bank() argument
234 val |= MCI_CTL2_CMCI_EN; in cmci_claim_bank()
235 wrmsrq(MSR_IA32_MCx_CTL2(bank), val); in cmci_claim_bank()
236 rdmsrq(MSR_IA32_MCx_CTL2(bank), val); in cmci_claim_bank()
239 if (!(val & MCI_CTL2_CMCI_EN)) { in cmci_claim_bank()
248 if ((val & MCI_CTL2_CMCI_THRESHOLD_MASK) == CMCI_STORM_THRESHOLD) { in cmci_claim_bank()
263 (val & MCI_CTL2_CMCI_THRESHOLD_MASK)) in cmci_claim_bank()
268 cmci_threshold[bank] = val & MCI_CTL2_CMCI_THRESHOLD_MASK; in cmci_claim_bank()
285 u64 val; in cmci_discover() local
288 if (cmci_skip_bank(i, &val)) in cmci_discover()
291 val = cmci_pick_threshold(val, &bios_zero_thresh); in cmci_discover()
292 cmci_claim_bank(i, val, bios_zero_thresh, &bios_wrong_thresh); in cmci_discover()
323 u64 val; in __cmci_disable_bank() local
327 rdmsrq(MSR_IA32_MCx_CTL2(bank), val); in __cmci_disable_bank()
328 val &= ~MCI_CTL2_CMCI_EN; in __cmci_disable_bank()
329 wrmsrq(MSR_IA32_MCx_CTL2(bank), val); in __cmci_disable_bank()
332 if ((val & MCI_CTL2_CMCI_THRESHOLD_MASK) == CMCI_STORM_THRESHOLD) in __cmci_disable_bank()
428 u64 val; in intel_init_lmce() local
433 rdmsrq(MSR_IA32_MCG_EXT_CTL, val); in intel_init_lmce()
435 if (!(val & MCG_EXT_CTL_LMCE_EN)) in intel_init_lmce()
436 wrmsrq(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN); in intel_init_lmce()
441 u64 val; in intel_clear_lmce() local
446 rdmsrq(MSR_IA32_MCG_EXT_CTL, val); in intel_clear_lmce()
447 val &= ~MCG_EXT_CTL_LMCE_EN; in intel_clear_lmce()
448 wrmsrq(MSR_IA32_MCG_EXT_CTL, val); in intel_clear_lmce()