Lines Matching refs:dev
62 pciauto_setup_bars(struct pci_dev *dev, int bar_limit) in pciauto_setup_bars() argument
74 pci_write_config_dword(dev, bar, 0xffffffff); in pciauto_setup_bars()
75 pci_read_config_dword(dev, bar, &bar_size); in pciauto_setup_bars()
103 pci_write_config_dword(dev, bar, *upper_limit); in pciauto_setup_bars()
112 pci_write_config_dword(dev, (bar+=4), 0x00000000); in pciauto_setup_bars()
122 pciauto_setup_irq(struct pci_controller* pci_ctrl,struct pci_dev *dev,int devfn) in pciauto_setup_irq() argument
127 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); in pciauto_setup_irq()
135 irq = pci_ctrl->map_irq(dev, PCI_SLOT(devfn), pin); in pciauto_setup_irq()
142 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); in pciauto_setup_irq()
147 pciauto_prescan_setup_bridge(struct pci_dev *dev, int current_bus, in pciauto_prescan_setup_bridge() argument
151 pci_write_config_byte(dev, PCI_PRIMARY_BUS, current_bus); in pciauto_prescan_setup_bridge()
152 pci_write_config_byte(dev, PCI_SECONDARY_BUS, sub_bus + 1); in pciauto_prescan_setup_bridge()
153 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, 0xff); in pciauto_prescan_setup_bridge()
164 pci_write_config_word(dev, PCI_MEMORY_LIMIT, in pciauto_prescan_setup_bridge()
166 pci_write_config_byte(dev, PCI_IO_LIMIT, in pciauto_prescan_setup_bridge()
168 pci_write_config_word(dev, PCI_IO_LIMIT_UPPER16, in pciauto_prescan_setup_bridge()
173 pciauto_postscan_setup_bridge(struct pci_dev *dev, int current_bus, int sub_bus, in pciauto_postscan_setup_bridge() argument
179 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, sub_bus); in pciauto_postscan_setup_bridge()
189 pci_write_config_word(dev, PCI_MEMORY_BASE, pciauto_upper_memspc >> 16); in pciauto_postscan_setup_bridge()
192 pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, in pciauto_postscan_setup_bridge()
197 pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, in pciauto_postscan_setup_bridge()
205 pci_write_config_byte(dev, PCI_IO_BASE, in pciauto_postscan_setup_bridge()
207 pci_write_config_word(dev, PCI_IO_BASE_UPPER16, in pciauto_postscan_setup_bridge()
211 pci_read_config_dword(dev, PCI_COMMAND, &cmdstat); in pciauto_postscan_setup_bridge()
212 pci_write_config_dword(dev, PCI_COMMAND, in pciauto_postscan_setup_bridge()
229 struct pci_dev *dev = &pciauto_dev; in pciauto_bus_scan() local
262 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type)) in pciauto_bus_scan()
267 pci_read_config_word(dev, PCI_VENDOR_ID, &vid); in pciauto_bus_scan()
274 pci_read_config_dword(dev, PCI_CLASS_REVISION, &pci_class); in pciauto_bus_scan()
284 pciauto_setup_bars(dev, PCI_BASE_ADDRESS_1); in pciauto_bus_scan()
286 pciauto_prescan_setup_bridge(dev, current_bus, sub_bus, in pciauto_bus_scan()
289 pciauto_postscan_setup_bridge(dev, current_bus, sub_bus, in pciauto_bus_scan()
302 pci_read_config_dword(dev, PCI_COMMAND, &cmdstat); in pciauto_bus_scan()
303 pci_write_config_dword(dev, PCI_COMMAND, in pciauto_bus_scan()
308 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80); in pciauto_bus_scan()
314 pciauto_setup_bars(dev, PCI_BASE_ADDRESS_5); in pciauto_bus_scan()
315 pciauto_setup_irq(pci_ctrl, dev, pci_devfn); in pciauto_bus_scan()