Lines Matching refs:pll
60 static inline int clk_pllv4_wait_lock(struct clk_pllv4 *pll) in clk_pllv4_wait_lock() argument
64 return readl_poll_timeout(pll->base + PLL_CSR_OFFSET, in clk_pllv4_wait_lock()
70 struct clk_pllv4 *pll = to_clk_pllv4(hw); in clk_pllv4_is_prepared() local
72 if (readl_relaxed(pll->base) & PLL_EN) in clk_pllv4_is_prepared()
81 struct clk_pllv4 *pll = to_clk_pllv4(hw); in clk_pllv4_recalc_rate() local
85 mult = readl_relaxed(pll->base + pll->cfg_offset); in clk_pllv4_recalc_rate()
89 mfn = readl_relaxed(pll->base + pll->num_offset); in clk_pllv4_recalc_rate()
90 mfd = readl_relaxed(pll->base + pll->denom_offset); in clk_pllv4_recalc_rate()
101 struct clk_pllv4 *pll = to_clk_pllv4(hw); in clk_pllv4_determine_rate() local
109 if (pll->use_mult_range) { in clk_pllv4_determine_rate()
165 static bool clk_pllv4_is_valid_mult(struct clk_pllv4 *pll, unsigned int mult) in clk_pllv4_is_valid_mult() argument
170 if (pll->use_mult_range) { in clk_pllv4_is_valid_mult()
187 struct clk_pllv4 *pll = to_clk_pllv4(hw); in clk_pllv4_set_rate() local
193 if (!clk_pllv4_is_valid_mult(pll, mult)) in clk_pllv4_set_rate()
204 val = readl_relaxed(pll->base + pll->cfg_offset); in clk_pllv4_set_rate()
207 writel_relaxed(val, pll->base + pll->cfg_offset); in clk_pllv4_set_rate()
209 writel_relaxed(mfn, pll->base + pll->num_offset); in clk_pllv4_set_rate()
210 writel_relaxed(mfd, pll->base + pll->denom_offset); in clk_pllv4_set_rate()
218 struct clk_pllv4 *pll = to_clk_pllv4(hw); in clk_pllv4_prepare() local
220 val = readl_relaxed(pll->base); in clk_pllv4_prepare()
222 writel_relaxed(val, pll->base); in clk_pllv4_prepare()
224 return clk_pllv4_wait_lock(pll); in clk_pllv4_prepare()
230 struct clk_pllv4 *pll = to_clk_pllv4(hw); in clk_pllv4_unprepare() local
232 val = readl_relaxed(pll->base); in clk_pllv4_unprepare()
234 writel_relaxed(val, pll->base); in clk_pllv4_unprepare()
249 struct clk_pllv4 *pll; in imx_clk_hw_pllv4() local
254 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in imx_clk_hw_pllv4()
255 if (!pll) in imx_clk_hw_pllv4()
258 pll->base = base; in imx_clk_hw_pllv4()
262 pll->cfg_offset = IMX8ULP_PLL_CFG_OFFSET; in imx_clk_hw_pllv4()
263 pll->num_offset = IMX8ULP_PLL_NUM_OFFSET; in imx_clk_hw_pllv4()
264 pll->denom_offset = IMX8ULP_PLL_DENOM_OFFSET; in imx_clk_hw_pllv4()
266 pll->use_mult_range = true; in imx_clk_hw_pllv4()
268 pll->cfg_offset = PLL_CFG_OFFSET; in imx_clk_hw_pllv4()
269 pll->num_offset = PLL_NUM_OFFSET; in imx_clk_hw_pllv4()
270 pll->denom_offset = PLL_DENOM_OFFSET; in imx_clk_hw_pllv4()
279 pll->hw.init = &init; in imx_clk_hw_pllv4()
281 hw = &pll->hw; in imx_clk_hw_pllv4()
284 kfree(pll); in imx_clk_hw_pllv4()