clk-exynos7885.c - OpenGrok cross reference for /drivers/clk/samsung/clk-exynos7885.c

Lines Matching refs:__initconst
91 static const unsigned long top_clk_regs[] __initconst = {
156 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
195 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
243 static const struct samsung_div_clock top_div_clks[] __initconst = {
301 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
343 static const struct samsung_cmu_info top_cmu_info __initconst = {  variable
413 static const unsigned long peri_clk_regs[] __initconst = {
470 static const struct samsung_mux_clock peri_mux_clks[] __initconst = {
491 static const struct samsung_gate_clock peri_gate_clks[] __initconst = {
566 static const struct samsung_cmu_info peri_cmu_info __initconst = {  variable
604 static const unsigned long core_clk_regs[] __initconst = {
627 static const struct samsung_mux_clock core_mux_clks[] __initconst = {
638 static const struct samsung_div_clock core_div_clks[] __initconst = {
643 static const struct samsung_gate_clock core_gate_clks[] __initconst = {
673 static const struct samsung_cmu_info core_cmu_info __initconst = {  variable
709 static const unsigned long fsys_clk_regs[] __initconst = {
731 static const struct samsung_pll_rate_table pll_usb_rate_table[] __initconst = {
735 static const struct samsung_pll_clock fsys_pll_clks[] __initconst = {
749 static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
768 static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
798 static const struct samsung_cmu_info fsys_cmu_info __initconst = {  variable