Lines Matching refs:cs_mode
1204 int cs_mode = 0; in umc_get_cs_mode() local
1207 cs_mode |= CS_EVEN_PRIMARY; in umc_get_cs_mode()
1210 cs_mode |= CS_ODD_PRIMARY; in umc_get_cs_mode()
1213 cs_mode |= CS_EVEN_SECONDARY; in umc_get_cs_mode()
1216 cs_mode |= CS_ODD_SECONDARY; in umc_get_cs_mode()
1229 cs_mode |= CS_3R_INTERLEAVE; in umc_get_cs_mode()
1232 return cs_mode; in umc_get_cs_mode()
1235 static int calculate_cs_size(u32 mask, unsigned int cs_mode) in calculate_cs_size() argument
1256 num_zero_bits = msb - weight - !!(cs_mode & CS_3R_INTERLEAVE); in calculate_cs_size()
1266 unsigned int cs_mode, int csrow_nr, int dimm) in __addr_mask_to_cs_size() argument
1274 size = calculate_cs_size(addr_mask, cs_mode); in __addr_mask_to_cs_size()
1277 size += calculate_cs_size(addr_mask_sec, cs_mode); in __addr_mask_to_cs_size()
1284 unsigned int cs_mode, int csrow_nr) in umc_addr_mask_to_cs_size() argument
1291 if (!cs_mode) in umc_addr_mask_to_cs_size()
1295 if (!(cs_mode & CS_EVEN) && !(csrow_nr & 1)) in umc_addr_mask_to_cs_size()
1299 if (!(cs_mode & CS_ODD) && (csrow_nr & 1)) in umc_addr_mask_to_cs_size()
1325 if (cs_mode & (CS_EVEN_PRIMARY | CS_ODD_PRIMARY)) in umc_addr_mask_to_cs_size()
1328 if (cs_mode & (CS_EVEN_SECONDARY | CS_ODD_SECONDARY)) in umc_addr_mask_to_cs_size()
1331 return __addr_mask_to_cs_size(addr_mask, addr_mask_sec, cs_mode, csrow_nr, dimm); in umc_addr_mask_to_cs_size()
1336 int dimm, size0, size1, cs0, cs1, cs_mode; in umc_debug_display_dimm_sizes() local
1344 cs_mode = umc_get_cs_mode(dimm, ctrl, pvt); in umc_debug_display_dimm_sizes()
1346 size0 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs0); in umc_debug_display_dimm_sizes()
1347 size1 = umc_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs1); in umc_debug_display_dimm_sizes()
1856 unsigned cs_mode, int cs_mask_nr) in k8_dbam_to_chip_select() argument
1861 WARN_ON(cs_mode > 11); in k8_dbam_to_chip_select()
1862 return ddr2_cs_size(cs_mode, dclr & WIDTH_128); in k8_dbam_to_chip_select()
1866 WARN_ON(cs_mode > 10); in k8_dbam_to_chip_select()
1892 diff = cs_mode/3 + (unsigned)(cs_mode > 5); in k8_dbam_to_chip_select()
1894 return 32 << (cs_mode - diff); in k8_dbam_to_chip_select()
1897 WARN_ON(cs_mode > 6); in k8_dbam_to_chip_select()
1898 return 32 << cs_mode; in k8_dbam_to_chip_select()
1960 unsigned cs_mode, int cs_mask_nr) in f10_dbam_to_chip_select() argument
1964 WARN_ON(cs_mode > 11); in f10_dbam_to_chip_select()
1967 return ddr3_cs_size(cs_mode, dclr & WIDTH_128); in f10_dbam_to_chip_select()
1969 return ddr2_cs_size(cs_mode, dclr & WIDTH_128); in f10_dbam_to_chip_select()
1976 unsigned cs_mode, int cs_mask_nr) in f15_dbam_to_chip_select() argument
1978 WARN_ON(cs_mode > 12); in f15_dbam_to_chip_select()
1980 return ddr3_cs_size(cs_mode, false); in f15_dbam_to_chip_select()
1985 unsigned cs_mode, int cs_mask_nr) in f15_m60h_dbam_to_chip_select() argument
1990 WARN_ON(cs_mode > 12); in f15_m60h_dbam_to_chip_select()
1993 if (cs_mode > 9) in f15_m60h_dbam_to_chip_select()
1996 cs_size = ddr4_cs_size(cs_mode); in f15_m60h_dbam_to_chip_select()
2002 cs_size = ddr3_lrdimm_cs_size(cs_mode, rank_multiply); in f15_m60h_dbam_to_chip_select()
2005 if (cs_mode == 0x1) in f15_m60h_dbam_to_chip_select()
2008 cs_size = ddr3_cs_size(cs_mode, false); in f15_m60h_dbam_to_chip_select()
2018 unsigned cs_mode, int cs_mask_nr) in f16_dbam_to_chip_select() argument
2020 WARN_ON(cs_mode > 12); in f16_dbam_to_chip_select()
2022 if (cs_mode == 6 || cs_mode == 8 || in f16_dbam_to_chip_select()
2023 cs_mode == 9 || cs_mode == 12) in f16_dbam_to_chip_select()
2026 return ddr3_cs_size(cs_mode, false); in f16_dbam_to_chip_select()
3051 u32 cs_mode, nr_pages; in dct_get_csrow_nr_pages() local
3054 cs_mode = DBAM_DIMM(csrow_nr, dbam); in dct_get_csrow_nr_pages()
3056 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr); in dct_get_csrow_nr_pages()
3060 csrow_nr, dct, cs_mode); in dct_get_csrow_nr_pages()
3069 u32 cs_mode, nr_pages; in umc_get_csrow_nr_pages() local
3071 cs_mode = umc_get_cs_mode(csrow_nr >> 1, dct, pvt); in umc_get_csrow_nr_pages()
3073 nr_pages = umc_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr); in umc_get_csrow_nr_pages()
3077 csrow_nr_orig, dct, cs_mode); in umc_get_csrow_nr_pages()
3527 unsigned int cs_mode, int csrow_nr) in gpu_addr_mask_to_cs_size() argument
3532 return __addr_mask_to_cs_size(addr_mask, addr_mask_sec, cs_mode, csrow_nr, csrow_nr >> 1); in gpu_addr_mask_to_cs_size()
3537 int size, cs_mode, cs = 0; in gpu_debug_display_dimm_sizes() local
3541 cs_mode = CS_EVEN_PRIMARY | CS_ODD_PRIMARY; in gpu_debug_display_dimm_sizes()
3544 size = gpu_addr_mask_to_cs_size(pvt, ctrl, cs_mode, cs); in gpu_debug_display_dimm_sizes()
3569 int cs_mode = CS_EVEN_PRIMARY | CS_ODD_PRIMARY; in gpu_get_csrow_nr_pages() local
3571 nr_pages = gpu_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr); in gpu_get_csrow_nr_pages()