Lines Matching refs:dct
104 static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) in f15h_select_dct() argument
110 reg |= dct; in f15h_select_dct()
128 static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, in amd64_read_dct_pci_cfg() argument
133 if (dct || offset >= 0x100) in amd64_read_dct_pci_cfg()
138 if (dct) { in amd64_read_dct_pci_cfg()
156 dct = (dct && pvt->model == 0x30) ? 3 : dct; in amd64_read_dct_pci_cfg()
157 f15h_select_dct(pvt, dct); in amd64_read_dct_pci_cfg()
161 if (dct) in amd64_read_dct_pci_cfg()
374 static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct, in get_cs_base_and_mask() argument
381 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
382 csmask = pvt->csels[dct].csmasks[csrow]; in get_cs_base_and_mask()
393 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
394 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
409 csbase = pvt->csels[dct].csbases[csrow]; in get_cs_base_and_mask()
410 csmask = pvt->csels[dct].csmasks[csrow >> 1]; in get_cs_base_and_mask()
430 #define for_each_chip_select(i, dct, pvt) \ argument
431 for (i = 0; i < pvt->csels[dct].b_cnt; i++)
433 #define chip_select_base(i, dct, pvt) \ argument
434 pvt->csels[dct].csbases[i]
436 #define for_each_chip_select_mask(i, dct, pvt) \ argument
437 for (i = 0; i < pvt->csels[dct].m_cnt; i++)
1855 static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in k8_dbam_to_chip_select() argument
1858 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in k8_dbam_to_chip_select()
1959 static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f10_dbam_to_chip_select() argument
1962 u32 dclr = dct ? pvt->dclr1 : pvt->dclr0; in f10_dbam_to_chip_select()
1975 static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f15_dbam_to_chip_select() argument
1984 static int f15_m60h_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f15_m60h_dbam_to_chip_select() argument
1988 u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr]; in f15_m60h_dbam_to_chip_select()
2017 static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct, in f16_dbam_to_chip_select() argument
2189 static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow) in f10_process_possible_spare() argument
2193 if (online_spare_swap_done(pvt, dct) && in f10_process_possible_spare()
2194 csrow == online_spare_bad_dramcs(pvt, dct)) { in f10_process_possible_spare()
2196 for_each_chip_select(tmp_cs, dct, pvt) { in f10_process_possible_spare()
2197 if (chip_select_base(tmp_cs, dct, pvt) & 0x2) { in f10_process_possible_spare()
2214 static int f1x_lookup_addr_in_dct(u64 in_addr, u8 nid, u8 dct) in f1x_lookup_addr_in_dct() argument
2228 edac_dbg(1, "input addr: 0x%llx, DCT: %d\n", in_addr, dct); in f1x_lookup_addr_in_dct()
2230 for_each_chip_select(csrow, dct, pvt) { in f1x_lookup_addr_in_dct()
2231 if (!csrow_enabled(csrow, dct, pvt)) in f1x_lookup_addr_in_dct()
2234 get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask); in f1x_lookup_addr_in_dct()
2249 cs_found = f10_process_possible_spare(pvt, dct, csrow); in f1x_lookup_addr_in_dct()
3048 static u32 dct_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr) in dct_get_csrow_nr_pages() argument
3050 u32 dbam = dct ? pvt->dbam1 : pvt->dbam0; in dct_get_csrow_nr_pages()
3056 nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr); in dct_get_csrow_nr_pages()
3060 csrow_nr, dct, cs_mode); in dct_get_csrow_nr_pages()
3066 static u32 umc_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig) in umc_get_csrow_nr_pages() argument
3071 cs_mode = umc_get_cs_mode(csrow_nr >> 1, dct, pvt); in umc_get_csrow_nr_pages()
3073 nr_pages = umc_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr); in umc_get_csrow_nr_pages()
3077 csrow_nr_orig, dct, cs_mode); in umc_get_csrow_nr_pages()
3566 static u32 gpu_get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr) in gpu_get_csrow_nr_pages() argument
3571 nr_pages = gpu_addr_mask_to_cs_size(pvt, dct, cs_mode, csrow_nr); in gpu_get_csrow_nr_pages()
3574 edac_dbg(0, "csrow: %d, channel: %d\n", csrow_nr, dct); in gpu_get_csrow_nr_pages()
3996 int cs = 0, dct = 0; in instance_has_memory() local
3998 for (dct = 0; dct < pvt->max_mcs; dct++) { in instance_has_memory()
3999 for_each_chip_select(cs, dct, pvt) in instance_has_memory()
4000 cs_enabled |= csrow_enabled(cs, dct, pvt); in instance_has_memory()