Lines Matching refs:m
14 static void (*decode_dram_ecc)(int node_id, struct mce *m);
289 static void decode_mc0_mce(struct mce *m) in decode_mc0_mce() argument
291 u16 ec = EC(m->status); in decode_mc0_mce()
292 u8 xec = XEC(m->status, xec_mask); in decode_mc0_mce()
399 static void decode_mc1_mce(struct mce *m) in decode_mc1_mce() argument
401 u16 ec = EC(m->status); in decode_mc1_mce()
402 u8 xec = XEC(m->status, xec_mask); in decode_mc1_mce()
410 bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58))); in decode_mc1_mce()
545 static void decode_mc2_mce(struct mce *m) in decode_mc2_mce() argument
547 u16 ec = EC(m->status); in decode_mc2_mce()
548 u8 xec = XEC(m->status, xec_mask); in decode_mc2_mce()
556 static void decode_mc3_mce(struct mce *m) in decode_mc3_mce() argument
558 u16 ec = EC(m->status); in decode_mc3_mce()
559 u8 xec = XEC(m->status, xec_mask); in decode_mc3_mce()
585 static void decode_mc4_mce(struct mce *m) in decode_mc4_mce() argument
587 unsigned int fam = x86_family(m->cpuid); in decode_mc4_mce()
588 int node_id = topology_amd_node_id(m->extcpu); in decode_mc4_mce()
589 u16 ec = EC(m->status); in decode_mc4_mce()
590 u8 xec = XEC(m->status, 0x1f); in decode_mc4_mce()
607 decode_dram_ecc(node_id, m); in decode_mc4_mce()
643 static void decode_mc5_mce(struct mce *m) in decode_mc5_mce() argument
645 unsigned int fam = x86_family(m->cpuid); in decode_mc5_mce()
646 u16 ec = EC(m->status); in decode_mc5_mce()
647 u8 xec = XEC(m->status, xec_mask); in decode_mc5_mce()
675 static void decode_mc6_mce(struct mce *m) in decode_mc6_mce() argument
677 u8 xec = XEC(m->status, xec_mask); in decode_mc6_mce()
733 static void decode_smca_error(struct mce *m) in decode_smca_error() argument
735 enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank); in decode_smca_error()
736 u8 xec = XEC(m->status, xec_mask); in decode_smca_error()
742 pr_emerg(HW_ERR "Bank %d is reserved.\n", m->bank); in decode_smca_error()
750 decode_dram_ecc(topology_amd_node_id(m->extcpu), m); in decode_smca_error()
777 static const char *decode_error_status(struct mce *m) in decode_error_status() argument
779 if (m->status & MCI_STATUS_UC) { in decode_error_status()
780 if (m->status & MCI_STATUS_PCC) in decode_error_status()
782 if (m->mcgstatus & MCG_STATUS_RIPV) in decode_error_status()
787 if (m->status & MCI_STATUS_DEFERRED) in decode_error_status()
796 struct mce *m = (struct mce *)data; in amd_decode_mce() local
797 struct mce_hw_err *err = to_mce_hw_err(m); in amd_decode_mce()
798 unsigned int fam = x86_family(m->cpuid); in amd_decode_mce()
802 if (m->kflags & MCE_HANDLED_CEC) in amd_decode_mce()
805 pr_emerg(HW_ERR "%s\n", decode_error_status(m)); in amd_decode_mce()
808 m->extcpu, in amd_decode_mce()
809 fam, x86_model(m->cpuid), x86_stepping(m->cpuid), in amd_decode_mce()
810 m->bank, in amd_decode_mce()
811 ((m->status & MCI_STATUS_OVER) ? "Over" : "-"), in amd_decode_mce()
812 ((m->status & MCI_STATUS_UC) ? "UE" : in amd_decode_mce()
813 (m->status & MCI_STATUS_DEFERRED) ? "-" : "CE"), in amd_decode_mce()
814 ((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"), in amd_decode_mce()
815 ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"), in amd_decode_mce()
816 ((m->status & MCI_STATUS_PCC) ? "PCC" : "-")); in amd_decode_mce()
819 rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(m->bank), &mca_config_lo, &dummy); in amd_decode_mce()
822 pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-")); in amd_decode_mce()
824 pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-")); in amd_decode_mce()
828 ecc = (m->status >> 45) & 0x3; in amd_decode_mce()
833 pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-")); in amd_decode_mce()
836 if (fam != 0x15 || m->bank != 4) in amd_decode_mce()
837 pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-")); in amd_decode_mce()
841 pr_cont("|%s", (m->status & MCI_STATUS_SCRUB ? "Scrub" : "-")); in amd_decode_mce()
843 pr_cont("]: 0x%016llx\n", m->status); in amd_decode_mce()
845 if (m->status & MCI_STATUS_ADDRV) in amd_decode_mce()
846 pr_emerg(HW_ERR "Error Addr: 0x%016llx\n", m->addr); in amd_decode_mce()
848 if (m->ppin) in amd_decode_mce()
849 pr_emerg(HW_ERR "PPIN: 0x%016llx\n", m->ppin); in amd_decode_mce()
852 pr_emerg(HW_ERR "IPID: 0x%016llx", m->ipid); in amd_decode_mce()
854 if (m->status & MCI_STATUS_SYNDV) { in amd_decode_mce()
855 pr_cont(", Syndrome: 0x%016llx\n", m->synd); in amd_decode_mce()
869 decode_smca_error(m); in amd_decode_mce()
873 if (m->tsc) in amd_decode_mce()
874 pr_emerg(HW_ERR "TSC: %llu\n", m->tsc); in amd_decode_mce()
880 switch (m->bank) { in amd_decode_mce()
882 decode_mc0_mce(m); in amd_decode_mce()
886 decode_mc1_mce(m); in amd_decode_mce()
890 decode_mc2_mce(m); in amd_decode_mce()
894 decode_mc3_mce(m); in amd_decode_mce()
898 decode_mc4_mce(m); in amd_decode_mce()
902 decode_mc5_mce(m); in amd_decode_mce()
906 decode_mc6_mce(m); in amd_decode_mce()
914 amd_decode_err_code(m->status & 0xffff); in amd_decode_mce()
916 m->kflags |= MCE_HANDLED_EDAC; in amd_decode_mce()