Lines Matching refs:GC
88 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); in kgd_program_sh_mem_settings()
89 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
151 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, in kgd_init_interrupts()
189 uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) -
224 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in kgd_hqd_load()
227 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_hqd_load()
228 WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]); in kgd_hqd_load()
234 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data); in kgd_hqd_load()
263 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, in kgd_hqd_load()
265 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in kgd_hqd_load()
267 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, in kgd_hqd_load()
269 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, in kgd_hqd_load()
273 WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1, in kgd_hqd_load()
278 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_RPTR, in kgd_hqd_load()
283 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data); in kgd_hqd_load()
352 (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \ in kgd_hqd_dump()
361 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); in kgd_hqd_dump()
362 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_hqd_dump()
482 act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in kgd_hqd_is_occupied()
487 if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) && in kgd_hqd_is_occupied()
488 high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI)) in kgd_hqd_is_occupied()
534 WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); in kgd_hqd_destroy()
607 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type); in kgd_hqd_destroy()
611 temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in kgd_hqd_destroy()
685 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val); in kgd_wave_control_execute()
686 WREG32_SOC15(GC, 0, mmSQ_CMD, sq_cmd); in kgd_wave_control_execute()
695 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in kgd_wave_control_execute()
738 uint32_t data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL)); in kgd_gfx_v10_set_wave_launch_stall()
744 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data); in kgd_gfx_v10_set_wave_launch_stall()
750 RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL)); in kgd_gfx_v10_set_wave_launch_stall()
770 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_CONFIG), data); in kgd_gfx_v10_enable_debug_trap()
771 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA0), 0); in kgd_gfx_v10_enable_debug_trap()
772 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_DATA1), 0); in kgd_gfx_v10_enable_debug_trap()
781 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); in kgd_gfx_v10_enable_debug_trap()
798 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); in kgd_gfx_v10_disable_debug_trap()
837 wave_cntl_prev = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL)); in kgd_gfx_v10_set_wave_launch_trap_override()
841 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK)); in kgd_gfx_v10_set_wave_launch_trap_override()
849 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), data); in kgd_gfx_v10_set_wave_launch_trap_override()
852 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), wave_cntl_prev); in kgd_gfx_v10_set_wave_launch_trap_override()
874 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL2), data); in kgd_gfx_v10_set_wave_launch_mode()
937 WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v10_set_address_watch()
945 WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_CNTL) + in kgd_gfx_v10_set_address_watch()
950 WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) + in kgd_gfx_v10_set_address_watch()
953 WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_L) + in kgd_gfx_v10_set_address_watch()
957 WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_ADDR_H) + in kgd_gfx_v10_set_address_watch()
960 WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_ADDR_L) + in kgd_gfx_v10_set_address_watch()
969 WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v10_set_address_watch()
977 WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_CNTL) + in kgd_gfx_v10_set_address_watch()
991 WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v10_clear_address_watch()
995 WREG32((SOC15_REG_OFFSET(GC, 0, mmSQ_WATCH0_CNTL) + in kgd_gfx_v10_clear_address_watch()
1021 *wait_times = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2)); in kgd_gfx_v10_get_iq_wait_times()
1044 *reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2); in kgd_gfx_v10_build_dequeue_wait_counts_packet_info()
1056 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO), in program_trap_handler_settings()
1058 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI), in program_trap_handler_settings()
1065 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO), in program_trap_handler_settings()
1067 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI), in program_trap_handler_settings()