Lines Matching refs:WREG32
48 WREG32(mmSRBM_GFX_CNTL, value); in lock_srbm()
53 WREG32(mmSRBM_GFX_CNTL, 0); in unlock_srbm()
79 WREG32(mmSH_MEM_CONFIG, sh_mem_config); in kgd_program_sh_mem_settings()
80 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base); in kgd_program_sh_mem_settings()
81 WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit); in kgd_program_sh_mem_settings()
82 WREG32(mmSH_MEM_BASES, sh_mem_bases); in kgd_program_sh_mem_settings()
100 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping); in kgd_set_pasid_vmid_mapping()
104 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid); in kgd_set_pasid_vmid_mapping()
107 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping); in kgd_set_pasid_vmid_mapping()
123 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | in kgd_init_interrupts()
180 WREG32(mmRLC_CP_SCHEDULERS, value); in kgd_hqd_load()
187 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); in kgd_hqd_load()
195 WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr); in kgd_hqd_load()
196 WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr); in kgd_hqd_load()
197 WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem); in kgd_hqd_load()
201 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); in kgd_hqd_load()
208 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data); in kgd_hqd_load()
218 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask); in kgd_hqd_load()
221 WREG32(mmCP_HQD_ACTIVE, data); in kgd_hqd_load()
273 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_hqd_sdma_load()
290 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); in kgd_hqd_sdma_load()
291 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load()
295 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data); in kgd_hqd_sdma_load()
297 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
300 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR, in kgd_hqd_sdma_load()
302 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); in kgd_hqd_sdma_load()
303 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI, in kgd_hqd_sdma_load()
305 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, in kgd_hqd_sdma_load()
307 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, in kgd_hqd_sdma_load()
312 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data); in kgd_hqd_sdma_load()
476 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); in kgd_hqd_destroy()
508 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp); in kgd_hqd_sdma_destroy()
521 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0); in kgd_hqd_sdma_destroy()
522 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, in kgd_hqd_sdma_destroy()
550 WREG32(mmGRBM_GFX_INDEX, gfx_index_val); in kgd_wave_control_execute()
551 WREG32(mmSQ_CMD, sq_cmd); in kgd_wave_control_execute()
560 WREG32(mmGRBM_GFX_INDEX, data); in kgd_wave_control_execute()
570 WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va); in set_scratch_backing_va()
581 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, in set_vm_context_page_table_base()