Lines Matching refs:GC
54 soc15_grbm_select(adev, mec, pipe, queue, vmid, GET_INST(GC, inst)); in kgd_gfx_v9_lock_srbm()
59 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst)); in kgd_gfx_v9_unlock_srbm()
94 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG, sh_mem_config); in kgd_gfx_v9_program_sh_mem_settings()
95 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmSH_MEM_BASES, sh_mem_bases); in kgd_gfx_v9_program_sh_mem_settings()
171 WREG32_SOC15(GC, GET_INST(GC, inst), mmCPC_INT_CNTL, in kgd_gfx_v9_init_interrupts()
238 hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR); in kgd_gfx_v9_hqd_load()
241 reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_gfx_v9_hqd_load()
248 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL, data); in kgd_gfx_v9_hqd_load()
277 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO, in kgd_gfx_v9_hqd_load()
279 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI, in kgd_gfx_v9_hqd_load()
281 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR, in kgd_gfx_v9_hqd_load()
283 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, in kgd_gfx_v9_hqd_load()
285 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_PQ_WPTR_POLL_CNTL1, in kgd_gfx_v9_hqd_load()
290 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR, in kgd_gfx_v9_hqd_load()
294 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE, data); in kgd_gfx_v9_hqd_load()
372 for (reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR); in kgd_gfx_v9_hqd_dump()
373 reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_gfx_v9_hqd_dump()
493 act = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE); in kgd_gfx_v9_hqd_is_occupied()
498 if (low == RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE) && in kgd_gfx_v9_hqd_is_occupied()
499 high == RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI)) in kgd_gfx_v9_hqd_is_occupied()
540 WREG32_FIELD15_RLC(GC, GET_INST(GC, inst), RLC_CP_SCHEDULERS, scheduler1, 0); in kgd_gfx_v9_hqd_destroy()
557 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_DEQUEUE_REQUEST, type); in kgd_gfx_v9_hqd_destroy()
561 temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE); in kgd_gfx_v9_hqd_destroy()
635 WREG32_SOC15_RLC_SHADOW(GC, GET_INST(GC, inst), mmGRBM_GFX_INDEX, gfx_index_val); in kgd_gfx_v9_wave_control_execute()
636 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_CMD, sq_cmd); in kgd_gfx_v9_wave_control_execute()
645 WREG32_SOC15_RLC_SHADOW(GC, GET_INST(GC, inst), mmGRBM_GFX_INDEX, data); in kgd_gfx_v9_wave_control_execute()
676 uint32_t data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL)); in kgd_gfx_v9_set_wave_launch_stall()
685 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), data); in kgd_gfx_v9_set_wave_launch_stall()
691 RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL)); in kgd_gfx_v9_set_wave_launch_stall()
709 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); in kgd_gfx_v9_enable_debug_trap()
732 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), 0); in kgd_gfx_v9_disable_debug_trap()
771 wave_cntl_prev = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL)); in kgd_gfx_v9_set_wave_launch_trap_override()
775 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK)); in kgd_gfx_v9_set_wave_launch_trap_override()
783 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_TRAP_MASK), data); in kgd_gfx_v9_set_wave_launch_trap_override()
786 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL), wave_cntl_prev); in kgd_gfx_v9_set_wave_launch_trap_override()
808 WREG32(SOC15_REG_OFFSET(GC, 0, mmSPI_GDBG_WAVE_CNTL2), data); in kgd_gfx_v9_set_wave_launch_mode()
854 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v9_set_address_watch()
858 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) + in kgd_gfx_v9_set_address_watch()
862 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_L) + in kgd_gfx_v9_set_address_watch()
872 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v9_set_address_watch()
886 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v9_clear_address_watch()
909 *wait_times = RREG32_SOC15_RLC(GC, GET_INST(GC, inst), in kgd_gfx_v9_get_iq_wait_times()
964 soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0, GET_INST(GC, inst)); in get_wave_count()
965 reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, GET_INST(GC, inst), in get_wave_count()
971 (RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL) & in get_wave_count()
1034 soc15_grbm_select(adev, 1, 0, 0, 0, GET_INST(GC, inst)); in kgd_gfx_v9_get_cu_occupancy()
1047 queue_map = RREG32_SOC15(GC, GET_INST(GC, inst), mmSPI_CSQ_WF_ACTIVE_STATUS); in kgd_gfx_v9_get_cu_occupancy()
1072 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst)); in kgd_gfx_v9_get_cu_occupancy()
1100 *reg_offset = SOC15_REG_OFFSET(GC, 0, mmCP_IQ_WAIT_TIME2); in kgd_gfx_v9_build_dequeue_wait_counts_packet_info()
1111 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_LO, in kgd_gfx_v9_program_trap_handler_settings()
1113 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_HI, in kgd_gfx_v9_program_trap_handler_settings()
1119 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_LO, in kgd_gfx_v9_program_trap_handler_settings()
1121 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_HI, in kgd_gfx_v9_program_trap_handler_settings()
1137 if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE)) in kgd_gfx_v9_hqd_get_pq_addr()
1140 low = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE); in kgd_gfx_v9_hqd_get_pq_addr()
1141 high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI); in kgd_gfx_v9_hqd_get_pq_addr()
1163 uint32_t temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE); in kgd_gfx_v9_hqd_dequeue_wait()
1185 if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE)) in kgd_gfx_v9_hqd_reset()
1188 low = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE); in kgd_gfx_v9_hqd_reset()
1189 high = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI); in kgd_gfx_v9_hqd_reset()
1201 WREG32_SOC15(GC, GET_INST(GC, inst), mmSPI_COMPUTE_QUEUE_RESET, 0x1); in kgd_gfx_v9_hqd_reset()
1211 WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, pipe_reset_data); in kgd_gfx_v9_hqd_reset()
1212 WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_MEC_CNTL, 0); in kgd_gfx_v9_hqd_reset()