Lines Matching refs:reg_dump
170 uint32_t *reg_dump, in amdgpu_cper_entry_fill_runtime_section() argument
194 section->ctx.reg_arr_size = sizeof(section->ctx.reg_dump); in amdgpu_cper_entry_fill_runtime_section()
196 memcpy(section->ctx.reg_dump, reg_dump, reg_count * sizeof(uint32_t)); in amdgpu_cper_entry_fill_runtime_section()
224 section->ctx.reg_arr_size = sizeof(section->ctx.reg_dump); in amdgpu_cper_entry_fill_bad_page_threshold_section()
227 section->ctx.reg_dump[CPER_ACA_REG_CTL_LO] = 0x1; in amdgpu_cper_entry_fill_bad_page_threshold_section()
228 section->ctx.reg_dump[CPER_ACA_REG_CTL_HI] = 0x0; in amdgpu_cper_entry_fill_bad_page_threshold_section()
229 section->ctx.reg_dump[CPER_ACA_REG_STATUS_LO] = 0x137; in amdgpu_cper_entry_fill_bad_page_threshold_section()
230 section->ctx.reg_dump[CPER_ACA_REG_STATUS_HI] = 0xB0000000; in amdgpu_cper_entry_fill_bad_page_threshold_section()
231 section->ctx.reg_dump[CPER_ACA_REG_ADDR_LO] = 0x0; in amdgpu_cper_entry_fill_bad_page_threshold_section()
232 section->ctx.reg_dump[CPER_ACA_REG_ADDR_HI] = 0x0; in amdgpu_cper_entry_fill_bad_page_threshold_section()
233 section->ctx.reg_dump[CPER_ACA_REG_MISC0_LO] = 0x0; in amdgpu_cper_entry_fill_bad_page_threshold_section()
234 section->ctx.reg_dump[CPER_ACA_REG_MISC0_HI] = 0x0; in amdgpu_cper_entry_fill_bad_page_threshold_section()
235 section->ctx.reg_dump[CPER_ACA_REG_CONFIG_LO] = 0x2; in amdgpu_cper_entry_fill_bad_page_threshold_section()
236 section->ctx.reg_dump[CPER_ACA_REG_CONFIG_HI] = 0x1ff; in amdgpu_cper_entry_fill_bad_page_threshold_section()
237 section->ctx.reg_dump[CPER_ACA_REG_IPID_LO] = 0x0; in amdgpu_cper_entry_fill_bad_page_threshold_section()
238 section->ctx.reg_dump[CPER_ACA_REG_IPID_HI] = 0x96; in amdgpu_cper_entry_fill_bad_page_threshold_section()
239 section->ctx.reg_dump[CPER_ACA_REG_SYND_LO] = 0x0; in amdgpu_cper_entry_fill_bad_page_threshold_section()
240 section->ctx.reg_dump[CPER_ACA_REG_SYND_HI] = 0x0; in amdgpu_cper_entry_fill_bad_page_threshold_section()