Lines Matching defs:amdgpu_gmc
211 struct amdgpu_gmc { struct
217 resource_size_t aper_size;
218 resource_size_t aper_base;
221 u64 mc_vram_size;
222 u64 visible_vram_size;
233 u64 agp_size;
234 u64 agp_start;
235 u64 agp_end;
244 u64 gart_size;
245 u64 gart_start;
246 u64 gart_end;
257 u64 vram_start;
258 u64 vram_end;
265 u64 fb_start;
266 u64 fb_end;
290 struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE]; argument
301 const struct amdgpu_gmc_funcs *gmc_funcs; argument
302 enum amdgpu_memory_partition requested_nps_mode;
303 uint32_t supported_nps_modes;
304 uint32_t reset_flags;
306 struct amdgpu_xgmi xgmi;
307 struct amdgpu_irq_src ecc_irq;
308 int noretry;
309 uint32_t xnack_flags;
311 uint32_t vmid0_page_table_block_size;
312 uint32_t vmid0_page_table_depth;
313 struct amdgpu_bo *pdb0_bo;
315 void *ptr_pdb0;
318 u64 mall_size;
319 uint32_t m_half_use;
322 int num_umc;
324 u64 VM_L2_CNTL;
325 u64 VM_L2_CNTL2;
326 u64 VM_DUMMY_PAGE_FAULT_CNTL;
327 u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32;
328 u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32;
329 u64 VM_L2_PROTECTION_FAULT_CNTL;
330 u64 VM_L2_PROTECTION_FAULT_CNTL2;
331 u64 VM_L2_PROTECTION_FAULT_MM_CNTL3;
332 u64 VM_L2_PROTECTION_FAULT_MM_CNTL4;
333 u64 VM_L2_PROTECTION_FAULT_ADDR_LO32;
357 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((… argument