Lines Matching refs:adev
35 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev) in amdgpu_mes_doorbell_process_slice() argument
42 static int amdgpu_mes_doorbell_init(struct amdgpu_device *adev) in amdgpu_mes_doorbell_init() argument
45 struct amdgpu_mes *mes = &adev->mes; in amdgpu_mes_doorbell_init()
50 dev_err(adev->dev, "Failed to allocate MES doorbell bitmap\n"); in amdgpu_mes_doorbell_init()
56 adev->mes.aggregated_doorbells[i] = mes->db_start_dw_offset + i * 2; in amdgpu_mes_doorbell_init()
63 static int amdgpu_mes_event_log_init(struct amdgpu_device *adev) in amdgpu_mes_event_log_init() argument
70 r = amdgpu_bo_create_kernel(adev, adev->mes.event_log_size, PAGE_SIZE, in amdgpu_mes_event_log_init()
72 &adev->mes.event_log_gpu_obj, in amdgpu_mes_event_log_init()
73 &adev->mes.event_log_gpu_addr, in amdgpu_mes_event_log_init()
74 &adev->mes.event_log_cpu_addr); in amdgpu_mes_event_log_init()
76 dev_warn(adev->dev, "failed to create MES event log buffer (%d)", r); in amdgpu_mes_event_log_init()
80 memset(adev->mes.event_log_cpu_addr, 0, adev->mes.event_log_size); in amdgpu_mes_event_log_init()
86 static void amdgpu_mes_doorbell_free(struct amdgpu_device *adev) in amdgpu_mes_doorbell_free() argument
88 bitmap_free(adev->mes.doorbell_bitmap); in amdgpu_mes_doorbell_free()
91 int amdgpu_mes_init(struct amdgpu_device *adev) in amdgpu_mes_init() argument
95 adev->mes.adev = adev; in amdgpu_mes_init()
97 idr_init(&adev->mes.pasid_idr); in amdgpu_mes_init()
98 idr_init(&adev->mes.gang_id_idr); in amdgpu_mes_init()
99 idr_init(&adev->mes.queue_id_idr); in amdgpu_mes_init()
100 ida_init(&adev->mes.doorbell_ida); in amdgpu_mes_init()
101 spin_lock_init(&adev->mes.queue_id_lock); in amdgpu_mes_init()
102 mutex_init(&adev->mes.mutex_hidden); in amdgpu_mes_init()
105 spin_lock_init(&adev->mes.ring_lock[i]); in amdgpu_mes_init()
107 adev->mes.total_max_queue = AMDGPU_FENCE_MES_QUEUE_ID_MASK; in amdgpu_mes_init()
108 adev->mes.vmid_mask_mmhub = 0xffffff00; in amdgpu_mes_init()
109 adev->mes.vmid_mask_gfxhub = adev->gfx.disable_kq ? 0xfffffffe : 0xffffff00; in amdgpu_mes_init()
111 num_pipes = adev->gfx.me.num_pipe_per_me * adev->gfx.me.num_me; in amdgpu_mes_init()
113 dev_warn(adev->dev, "more gfx pipes than supported by MES! (%d vs %d)\n", in amdgpu_mes_init()
119 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= in amdgpu_mes_init()
127 adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ? 0xFF : 0xFE; in amdgpu_mes_init()
134 adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ? 0x3 : 0x2; in amdgpu_mes_init()
137 num_pipes = adev->gfx.mec.num_pipe_per_mec * adev->gfx.mec.num_mec; in amdgpu_mes_init()
139 dev_warn(adev->dev, "more compute pipes than supported by MES! (%d vs %d)\n", in amdgpu_mes_init()
145 adev->mes.compute_hqd_mask[i] = adev->gfx.disable_kq ? 0xF : 0xC; in amdgpu_mes_init()
148 num_pipes = adev->sdma.num_instances; in amdgpu_mes_init()
150 dev_warn(adev->dev, "more SDMA pipes than supported by MES! (%d vs %d)\n", in amdgpu_mes_init()
156 adev->mes.sdma_hqd_mask[i] = 0xfc; in amdgpu_mes_init()
160 r = amdgpu_device_wb_get(adev, &adev->mes.sch_ctx_offs[i]); in amdgpu_mes_init()
162 dev_err(adev->dev, in amdgpu_mes_init()
167 adev->mes.sch_ctx_gpu_addr[i] = in amdgpu_mes_init()
168 adev->wb.gpu_addr + (adev->mes.sch_ctx_offs[i] * 4); in amdgpu_mes_init()
169 adev->mes.sch_ctx_ptr[i] = in amdgpu_mes_init()
170 (uint64_t *)&adev->wb.wb[adev->mes.sch_ctx_offs[i]]; in amdgpu_mes_init()
172 r = amdgpu_device_wb_get(adev, in amdgpu_mes_init()
173 &adev->mes.query_status_fence_offs[i]); in amdgpu_mes_init()
175 dev_err(adev->dev, in amdgpu_mes_init()
180 adev->mes.query_status_fence_gpu_addr[i] = adev->wb.gpu_addr + in amdgpu_mes_init()
181 (adev->mes.query_status_fence_offs[i] * 4); in amdgpu_mes_init()
182 adev->mes.query_status_fence_ptr[i] = in amdgpu_mes_init()
183 (uint64_t *)&adev->wb.wb[adev->mes.query_status_fence_offs[i]]; in amdgpu_mes_init()
186 r = amdgpu_mes_doorbell_init(adev); in amdgpu_mes_init()
190 r = amdgpu_mes_event_log_init(adev); in amdgpu_mes_init()
197 amdgpu_mes_doorbell_free(adev); in amdgpu_mes_init()
200 if (adev->mes.sch_ctx_ptr[i]) in amdgpu_mes_init()
201 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]); in amdgpu_mes_init()
202 if (adev->mes.query_status_fence_ptr[i]) in amdgpu_mes_init()
203 amdgpu_device_wb_free(adev, in amdgpu_mes_init()
204 adev->mes.query_status_fence_offs[i]); in amdgpu_mes_init()
207 idr_destroy(&adev->mes.pasid_idr); in amdgpu_mes_init()
208 idr_destroy(&adev->mes.gang_id_idr); in amdgpu_mes_init()
209 idr_destroy(&adev->mes.queue_id_idr); in amdgpu_mes_init()
210 ida_destroy(&adev->mes.doorbell_ida); in amdgpu_mes_init()
211 mutex_destroy(&adev->mes.mutex_hidden); in amdgpu_mes_init()
215 void amdgpu_mes_fini(struct amdgpu_device *adev) in amdgpu_mes_fini() argument
219 amdgpu_bo_free_kernel(&adev->mes.event_log_gpu_obj, in amdgpu_mes_fini()
220 &adev->mes.event_log_gpu_addr, in amdgpu_mes_fini()
221 &adev->mes.event_log_cpu_addr); in amdgpu_mes_fini()
224 if (adev->mes.sch_ctx_ptr[i]) in amdgpu_mes_fini()
225 amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]); in amdgpu_mes_fini()
226 if (adev->mes.query_status_fence_ptr[i]) in amdgpu_mes_fini()
227 amdgpu_device_wb_free(adev, in amdgpu_mes_fini()
228 adev->mes.query_status_fence_offs[i]); in amdgpu_mes_fini()
231 amdgpu_mes_doorbell_free(adev); in amdgpu_mes_fini()
233 idr_destroy(&adev->mes.pasid_idr); in amdgpu_mes_fini()
234 idr_destroy(&adev->mes.gang_id_idr); in amdgpu_mes_fini()
235 idr_destroy(&adev->mes.queue_id_idr); in amdgpu_mes_fini()
236 ida_destroy(&adev->mes.doorbell_ida); in amdgpu_mes_fini()
237 mutex_destroy(&adev->mes.mutex_hidden); in amdgpu_mes_fini()
240 int amdgpu_mes_suspend(struct amdgpu_device *adev) in amdgpu_mes_suspend() argument
245 if (!amdgpu_mes_suspend_resume_all_supported(adev)) in amdgpu_mes_suspend()
255 amdgpu_mes_lock(&adev->mes); in amdgpu_mes_suspend()
256 r = adev->mes.funcs->suspend_gang(&adev->mes, &input); in amdgpu_mes_suspend()
257 amdgpu_mes_unlock(&adev->mes); in amdgpu_mes_suspend()
259 dev_err(adev->dev, "failed to suspend all gangs"); in amdgpu_mes_suspend()
264 int amdgpu_mes_resume(struct amdgpu_device *adev) in amdgpu_mes_resume() argument
269 if (!amdgpu_mes_suspend_resume_all_supported(adev)) in amdgpu_mes_resume()
279 amdgpu_mes_lock(&adev->mes); in amdgpu_mes_resume()
280 r = adev->mes.funcs->resume_gang(&adev->mes, &input); in amdgpu_mes_resume()
281 amdgpu_mes_unlock(&adev->mes); in amdgpu_mes_resume()
283 dev_err(adev->dev, "failed to resume all gangs"); in amdgpu_mes_resume()
288 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, in amdgpu_mes_map_legacy_queue() argument
303 amdgpu_mes_lock(&adev->mes); in amdgpu_mes_map_legacy_queue()
304 r = adev->mes.funcs->map_legacy_queue(&adev->mes, &queue_input); in amdgpu_mes_map_legacy_queue()
305 amdgpu_mes_unlock(&adev->mes); in amdgpu_mes_map_legacy_queue()
307 dev_err(adev->dev, "failed to map legacy queue\n"); in amdgpu_mes_map_legacy_queue()
312 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, in amdgpu_mes_unmap_legacy_queue() argument
328 amdgpu_mes_lock(&adev->mes); in amdgpu_mes_unmap_legacy_queue()
329 r = adev->mes.funcs->unmap_legacy_queue(&adev->mes, &queue_input); in amdgpu_mes_unmap_legacy_queue()
330 amdgpu_mes_unlock(&adev->mes); in amdgpu_mes_unmap_legacy_queue()
332 dev_err(adev->dev, "failed to unmap legacy queue\n"); in amdgpu_mes_unmap_legacy_queue()
337 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, in amdgpu_mes_reset_legacy_queue() argument
360 amdgpu_mes_lock(&adev->mes); in amdgpu_mes_reset_legacy_queue()
361 r = adev->mes.funcs->reset_hw_queue(&adev->mes, &queue_input); in amdgpu_mes_reset_legacy_queue()
362 amdgpu_mes_unlock(&adev->mes); in amdgpu_mes_reset_legacy_queue()
364 dev_err(adev->dev, "failed to reset legacy queue\n"); in amdgpu_mes_reset_legacy_queue()
369 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg) in amdgpu_mes_rreg() argument
377 if (amdgpu_device_wb_get(adev, &addr_offset)) { in amdgpu_mes_rreg()
378 dev_err(adev->dev, "critical bug! too many mes readers\n"); in amdgpu_mes_rreg()
381 read_val_gpu_addr = adev->wb.gpu_addr + (addr_offset * 4); in amdgpu_mes_rreg()
382 read_val_ptr = (uint32_t *)&adev->wb.wb[addr_offset]; in amdgpu_mes_rreg()
387 if (!adev->mes.funcs->misc_op) { in amdgpu_mes_rreg()
388 dev_err(adev->dev, "mes rreg is not supported!\n"); in amdgpu_mes_rreg()
392 amdgpu_mes_lock(&adev->mes); in amdgpu_mes_rreg()
393 r = adev->mes.funcs->misc_op(&adev->mes, &op_input); in amdgpu_mes_rreg()
394 amdgpu_mes_unlock(&adev->mes); in amdgpu_mes_rreg()
396 dev_err(adev->dev, "failed to read reg (0x%x)\n", reg); in amdgpu_mes_rreg()
402 amdgpu_device_wb_free(adev, addr_offset); in amdgpu_mes_rreg()
406 int amdgpu_mes_wreg(struct amdgpu_device *adev, in amdgpu_mes_wreg() argument
416 if (!adev->mes.funcs->misc_op) { in amdgpu_mes_wreg()
417 dev_err(adev->dev, "mes wreg is not supported!\n"); in amdgpu_mes_wreg()
422 amdgpu_mes_lock(&adev->mes); in amdgpu_mes_wreg()
423 r = adev->mes.funcs->misc_op(&adev->mes, &op_input); in amdgpu_mes_wreg()
424 amdgpu_mes_unlock(&adev->mes); in amdgpu_mes_wreg()
426 dev_err(adev->dev, "failed to write reg (0x%x)\n", reg); in amdgpu_mes_wreg()
432 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, in amdgpu_mes_reg_write_reg_wait() argument
445 if (!adev->mes.funcs->misc_op) { in amdgpu_mes_reg_write_reg_wait()
446 dev_err(adev->dev, "mes reg_write_reg_wait is not supported!\n"); in amdgpu_mes_reg_write_reg_wait()
451 amdgpu_mes_lock(&adev->mes); in amdgpu_mes_reg_write_reg_wait()
452 r = adev->mes.funcs->misc_op(&adev->mes, &op_input); in amdgpu_mes_reg_write_reg_wait()
453 amdgpu_mes_unlock(&adev->mes); in amdgpu_mes_reg_write_reg_wait()
455 dev_err(adev->dev, "failed to reg_write_reg_wait\n"); in amdgpu_mes_reg_write_reg_wait()
461 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, in amdgpu_mes_set_shader_debugger() argument
471 if (!adev->mes.funcs->misc_op) { in amdgpu_mes_set_shader_debugger()
472 dev_err(adev->dev, in amdgpu_mes_set_shader_debugger()
489 if (((adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK) >> in amdgpu_mes_set_shader_debugger()
493 amdgpu_mes_lock(&adev->mes); in amdgpu_mes_set_shader_debugger()
495 r = adev->mes.funcs->misc_op(&adev->mes, &op_input); in amdgpu_mes_set_shader_debugger()
497 dev_err(adev->dev, "failed to set_shader_debugger\n"); in amdgpu_mes_set_shader_debugger()
499 amdgpu_mes_unlock(&adev->mes); in amdgpu_mes_set_shader_debugger()
504 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, in amdgpu_mes_flush_shader_debugger() argument
510 if (!adev->mes.funcs->misc_op) { in amdgpu_mes_flush_shader_debugger()
511 dev_err(adev->dev, in amdgpu_mes_flush_shader_debugger()
520 amdgpu_mes_lock(&adev->mes); in amdgpu_mes_flush_shader_debugger()
522 r = adev->mes.funcs->misc_op(&adev->mes, &op_input); in amdgpu_mes_flush_shader_debugger()
524 dev_err(adev->dev, "failed to set_shader_debugger\n"); in amdgpu_mes_flush_shader_debugger()
526 amdgpu_mes_unlock(&adev->mes); in amdgpu_mes_flush_shader_debugger()
531 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, in amdgpu_mes_get_aggregated_doorbell_index() argument
534 return adev->mes.aggregated_doorbells[prio]; in amdgpu_mes_get_aggregated_doorbell_index()
537 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe) in amdgpu_mes_init_microcode() argument
547 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, in amdgpu_mes_init_microcode()
549 if (adev->enable_uni_mes) { in amdgpu_mes_init_microcode()
552 } else if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) && in amdgpu_mes_init_microcode()
553 amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0)) { in amdgpu_mes_init_microcode()
564 r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe], AMDGPU_UCODE_REQUIRED, in amdgpu_mes_init_microcode()
567 dev_info(adev->dev, "try to fall back to %s_mes.bin\n", ucode_prefix); in amdgpu_mes_init_microcode()
568 r = amdgpu_ucode_request(adev, &adev->mes.fw[pipe], in amdgpu_mes_init_microcode()
577 adev->mes.fw[pipe]->data; in amdgpu_mes_init_microcode()
578 adev->mes.uc_start_addr[pipe] = in amdgpu_mes_init_microcode()
581 adev->mes.data_start_addr[pipe] = in amdgpu_mes_init_microcode()
584 ucode_ptr = (u32 *)(adev->mes.fw[pipe]->data + in amdgpu_mes_init_microcode()
586 adev->mes.fw_version[pipe] = in amdgpu_mes_init_microcode()
589 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { in amdgpu_mes_init_microcode()
600 info = &adev->firmware.ucode[ucode]; in amdgpu_mes_init_microcode()
602 info->fw = adev->mes.fw[pipe]; in amdgpu_mes_init_microcode()
603 adev->firmware.fw_size += in amdgpu_mes_init_microcode()
607 info = &adev->firmware.ucode[ucode_data]; in amdgpu_mes_init_microcode()
609 info->fw = adev->mes.fw[pipe]; in amdgpu_mes_init_microcode()
610 adev->firmware.fw_size += in amdgpu_mes_init_microcode()
617 amdgpu_ucode_release(&adev->mes.fw[pipe]); in amdgpu_mes_init_microcode()
621 bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev) in amdgpu_mes_suspend_resume_all_supported() argument
623 uint32_t mes_rev = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; in amdgpu_mes_suspend_resume_all_supported()
626 if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) && in amdgpu_mes_suspend_resume_all_supported()
627 amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0) && in amdgpu_mes_suspend_resume_all_supported()
635 static int amdgpu_mes_set_enforce_isolation(struct amdgpu_device *adev, in amdgpu_mes_set_enforce_isolation() argument
644 if (!adev->mes.funcs->misc_op) { in amdgpu_mes_set_enforce_isolation()
645 dev_err(adev->dev, "mes change config is not supported!\n"); in amdgpu_mes_set_enforce_isolation()
650 amdgpu_mes_lock(&adev->mes); in amdgpu_mes_set_enforce_isolation()
651 r = adev->mes.funcs->misc_op(&adev->mes, &op_input); in amdgpu_mes_set_enforce_isolation()
652 amdgpu_mes_unlock(&adev->mes); in amdgpu_mes_set_enforce_isolation()
654 dev_err(adev->dev, "failed to change_config.\n"); in amdgpu_mes_set_enforce_isolation()
660 int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev) in amdgpu_mes_update_enforce_isolation() argument
664 if (adev->enable_mes && adev->gfx.enable_cleaner_shader) { in amdgpu_mes_update_enforce_isolation()
665 mutex_lock(&adev->enforce_isolation_mutex); in amdgpu_mes_update_enforce_isolation()
666 for (i = 0; i < (adev->xcp_mgr ? adev->xcp_mgr->num_xcps : 1); i++) { in amdgpu_mes_update_enforce_isolation()
667 if (adev->enforce_isolation[i] == AMDGPU_ENFORCE_ISOLATION_ENABLE) in amdgpu_mes_update_enforce_isolation()
668 r |= amdgpu_mes_set_enforce_isolation(adev, i, true); in amdgpu_mes_update_enforce_isolation()
670 r |= amdgpu_mes_set_enforce_isolation(adev, i, false); in amdgpu_mes_update_enforce_isolation()
672 mutex_unlock(&adev->enforce_isolation_mutex); in amdgpu_mes_update_enforce_isolation()
681 struct amdgpu_device *adev = m->private; in amdgpu_debugfs_mes_event_log_show() local
682 uint32_t *mem = (uint32_t *)(adev->mes.event_log_cpu_addr); in amdgpu_debugfs_mes_event_log_show()
685 mem, adev->mes.event_log_size, false); in amdgpu_debugfs_mes_event_log_show()
694 void amdgpu_debugfs_mes_event_log_init(struct amdgpu_device *adev) in amdgpu_debugfs_mes_event_log_init() argument
698 struct drm_minor *minor = adev_to_drm(adev)->primary; in amdgpu_debugfs_mes_event_log_init()
700 if (adev->enable_mes && amdgpu_mes_log_enable) in amdgpu_debugfs_mes_event_log_init()
702 adev, &amdgpu_debugfs_mes_event_log_fops); in amdgpu_debugfs_mes_event_log_init()