Lines Matching refs:control
173 struct amdgpu_ras_eeprom_control *control) in __get_eeprom_i2c_addr() argument
178 if (!control) in __get_eeprom_i2c_addr()
191 control->i2c_address = ((u32) i2c_addr) << 16; in __get_eeprom_i2c_addr()
200 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
204 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
206 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
209 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
214 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
216 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
221 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
223 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
229 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
262 static int __write_table_header(struct amdgpu_ras_eeprom_control *control) in __write_table_header() argument
265 struct amdgpu_device *adev = to_amdgpu_device(control); in __write_table_header()
269 __encode_table_header_to_buf(&control->tbl_hdr, buf); in __write_table_header()
274 control->i2c_address + in __write_table_header()
275 control->ras_header_offset, in __write_table_header()
319 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control) in __write_table_ras_info() argument
321 struct amdgpu_device *adev = to_amdgpu_device(control); in __write_table_ras_info()
332 __encode_table_ras_info_to_buf(&control->tbl_rai, buf); in __write_table_ras_info()
337 control->i2c_address + in __write_table_ras_info()
338 control->ras_info_offset, in __write_table_ras_info()
358 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control) in __calc_hdr_byte_sum() argument
365 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); in __calc_hdr_byte_sum()
366 pp = (u8 *) &control->tbl_hdr; in __calc_hdr_byte_sum()
374 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control) in __calc_ras_info_byte_sum() argument
380 sz = sizeof(control->tbl_rai); in __calc_ras_info_byte_sum()
381 pp = (u8 *) &control->tbl_rai; in __calc_ras_info_byte_sum()
390 struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_correct_header_tag() argument
393 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_correct_header_tag()
405 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_correct_header_tag()
408 res = __write_table_header(control); in amdgpu_ras_eeprom_correct_header_tag()
409 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_correct_header_tag()
414 static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_set_eeprom_table_version() argument
416 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_set_eeprom_table_version()
417 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_set_eeprom_table_version()
440 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_reset_table() argument
442 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_reset_table()
443 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_reset_table()
444 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; in amdgpu_ras_eeprom_reset_table()
449 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_reset_table()
452 amdgpu_ras_set_eeprom_table_version(control); in amdgpu_ras_eeprom_reset_table()
471 csum = __calc_hdr_byte_sum(control); in amdgpu_ras_eeprom_reset_table()
473 csum += __calc_ras_info_byte_sum(control); in amdgpu_ras_eeprom_reset_table()
476 res = __write_table_header(control); in amdgpu_ras_eeprom_reset_table()
478 res = __write_table_ras_info(control); in amdgpu_ras_eeprom_reset_table()
480 control->ras_num_recs = 0; in amdgpu_ras_eeprom_reset_table()
481 control->ras_num_bad_pages = 0; in amdgpu_ras_eeprom_reset_table()
482 control->ras_num_mca_recs = 0; in amdgpu_ras_eeprom_reset_table()
483 control->ras_num_pa_recs = 0; in amdgpu_ras_eeprom_reset_table()
484 control->ras_fri = 0; in amdgpu_ras_eeprom_reset_table()
486 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_bad_pages); in amdgpu_ras_eeprom_reset_table()
488 control->bad_channel_bitmap = 0; in amdgpu_ras_eeprom_reset_table()
489 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); in amdgpu_ras_eeprom_reset_table()
492 amdgpu_ras_debugfs_set_ret_size(control); in amdgpu_ras_eeprom_reset_table()
494 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_reset_table()
500 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control, in __encode_table_record_to_buf() argument
528 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control, in __decode_table_record_from_buf() argument
599 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control, in __amdgpu_ras_eeprom_write() argument
602 struct amdgpu_device *adev = to_amdgpu_device(control); in __amdgpu_ras_eeprom_write()
610 control->i2c_address + in __amdgpu_ras_eeprom_write()
611 RAS_INDEX_TO_OFFSET(control, fri), in __amdgpu_ras_eeprom_write()
631 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_append_table() argument
635 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control)); in amdgpu_ras_eeprom_append_table()
636 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_append_table()
649 __encode_table_record_to_buf(control, &record[i], pp); in amdgpu_ras_eeprom_append_table()
652 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && in amdgpu_ras_eeprom_append_table()
653 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { in amdgpu_ras_eeprom_append_table()
654 control->bad_channel_bitmap |= 1 << record[i].mem_channel; in amdgpu_ras_eeprom_append_table()
686 a = control->ras_fri + control->ras_num_recs; in amdgpu_ras_eeprom_append_table()
688 if (b < control->ras_max_record_count) { in amdgpu_ras_eeprom_append_table()
689 res = __amdgpu_ras_eeprom_write(control, buf, a, num); in amdgpu_ras_eeprom_append_table()
690 } else if (a < control->ras_max_record_count) { in amdgpu_ras_eeprom_append_table()
693 g0 = control->ras_max_record_count - a; in amdgpu_ras_eeprom_append_table()
694 g1 = b % control->ras_max_record_count + 1; in amdgpu_ras_eeprom_append_table()
695 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); in amdgpu_ras_eeprom_append_table()
698 res = __amdgpu_ras_eeprom_write(control, in amdgpu_ras_eeprom_append_table()
703 if (g1 > control->ras_fri) in amdgpu_ras_eeprom_append_table()
704 control->ras_fri = g1 % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
706 a %= control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
707 b %= control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
711 res = __amdgpu_ras_eeprom_write(control, buf, a, num); in amdgpu_ras_eeprom_append_table()
714 if (b >= control->ras_fri) in amdgpu_ras_eeprom_append_table()
715 control->ras_fri = (b + 1) % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
723 g0 = control->ras_max_record_count - a; in amdgpu_ras_eeprom_append_table()
725 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); in amdgpu_ras_eeprom_append_table()
728 res = __amdgpu_ras_eeprom_write(control, in amdgpu_ras_eeprom_append_table()
733 control->ras_fri = g1 % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
736 control->ras_num_recs = 1 + (control->ras_max_record_count + b in amdgpu_ras_eeprom_append_table()
737 - control->ras_fri) in amdgpu_ras_eeprom_append_table()
738 % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
742 control->ras_num_pa_recs += num; in amdgpu_ras_eeprom_append_table()
744 control->ras_num_mca_recs += num; in amdgpu_ras_eeprom_append_table()
746 control->ras_num_bad_pages = control->ras_num_pa_recs + in amdgpu_ras_eeprom_append_table()
747 control->ras_num_mca_recs * adev->umc.retire_unit; in amdgpu_ras_eeprom_append_table()
754 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_update_header() argument
756 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_update_header()
765 control->ras_num_bad_pages > ras->bad_page_cnt_threshold) { in amdgpu_ras_eeprom_update_header()
768 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_update_header()
771 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; in amdgpu_ras_eeprom_update_header()
772 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) { in amdgpu_ras_eeprom_update_header()
773 control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD; in amdgpu_ras_eeprom_update_header()
774 control->tbl_rai.health_percent = 0; in amdgpu_ras_eeprom_update_header()
782 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) in amdgpu_ras_eeprom_update_header()
783 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + in amdgpu_ras_eeprom_update_header()
785 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in amdgpu_ras_eeprom_update_header()
787 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + in amdgpu_ras_eeprom_update_header()
788 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in amdgpu_ras_eeprom_update_header()
789 control->tbl_hdr.checksum = 0; in amdgpu_ras_eeprom_update_header()
791 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in amdgpu_ras_eeprom_update_header()
792 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); in amdgpu_ras_eeprom_update_header()
796 control->tbl_hdr.tbl_size); in amdgpu_ras_eeprom_update_header()
803 control->i2c_address + in amdgpu_ras_eeprom_update_header()
804 control->ras_record_offset, in amdgpu_ras_eeprom_update_header()
822 control->tbl_hdr.version >= RAS_TABLE_VER_V2_1 && in amdgpu_ras_eeprom_update_header()
823 control->ras_num_bad_pages <= ras->bad_page_cnt_threshold) in amdgpu_ras_eeprom_update_header()
824 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold - in amdgpu_ras_eeprom_update_header()
825 control->ras_num_bad_pages) * 100) / in amdgpu_ras_eeprom_update_header()
834 csum += __calc_hdr_byte_sum(control); in amdgpu_ras_eeprom_update_header()
835 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) in amdgpu_ras_eeprom_update_header()
836 csum += __calc_ras_info_byte_sum(control); in amdgpu_ras_eeprom_update_header()
839 control->tbl_hdr.checksum = csum; in amdgpu_ras_eeprom_update_header()
840 res = __write_table_header(control); in amdgpu_ras_eeprom_update_header()
841 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1) in amdgpu_ras_eeprom_update_header()
842 res = __write_table_ras_info(control); in amdgpu_ras_eeprom_update_header()
861 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_append() argument
865 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_append()
875 } else if (num > control->ras_max_record_count) { in amdgpu_ras_eeprom_append()
878 num, control->ras_max_record_count); in amdgpu_ras_eeprom_append()
889 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_append()
891 res = amdgpu_ras_eeprom_append_table(control, record, num); in amdgpu_ras_eeprom_append()
893 res = amdgpu_ras_eeprom_update_header(control); in amdgpu_ras_eeprom_append()
895 amdgpu_ras_debugfs_set_ret_size(control); in amdgpu_ras_eeprom_append()
897 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_append()
916 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, in __amdgpu_ras_eeprom_read() argument
919 struct amdgpu_device *adev = to_amdgpu_device(control); in __amdgpu_ras_eeprom_read()
927 control->i2c_address + in __amdgpu_ras_eeprom_read()
928 RAS_INDEX_TO_OFFSET(control, fri), in __amdgpu_ras_eeprom_read()
958 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_read() argument
962 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_read()
974 } else if (num > control->ras_num_recs) { in amdgpu_ras_eeprom_read()
976 num, control->ras_num_recs); in amdgpu_ras_eeprom_read()
1004 g0 = control->ras_fri + num - 1; in amdgpu_ras_eeprom_read()
1005 g1 = g0 % control->ras_max_record_count; in amdgpu_ras_eeprom_read()
1006 if (g0 < control->ras_max_record_count) { in amdgpu_ras_eeprom_read()
1010 g0 = control->ras_max_record_count - control->ras_fri; in amdgpu_ras_eeprom_read()
1014 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_read()
1015 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0); in amdgpu_ras_eeprom_read()
1019 res = __amdgpu_ras_eeprom_read(control, in amdgpu_ras_eeprom_read()
1032 __decode_table_record_from_buf(control, &record[i], pp); in amdgpu_ras_eeprom_read()
1035 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && in amdgpu_ras_eeprom_read()
1036 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { in amdgpu_ras_eeprom_read()
1037 control->bad_channel_bitmap |= 1 << record[i].mem_channel; in amdgpu_ras_eeprom_read()
1043 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_read()
1048 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_max_record_count() argument
1051 amdgpu_ras_set_eeprom_table_version(control); in amdgpu_ras_eeprom_max_record_count()
1053 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) in amdgpu_ras_eeprom_max_record_count()
1065 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; in amdgpu_ras_debugfs_eeprom_size_read() local
1072 if (!ras || !control) { in amdgpu_ras_debugfs_eeprom_size_read()
1076 RAS_TBL_SIZE_BYTES, control->ras_max_record_count); in amdgpu_ras_debugfs_eeprom_size_read()
1113 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_debugfs_table_size() argument
1116 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs; in amdgpu_ras_debugfs_table_size()
1119 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_debugfs_set_ret_size() argument
1121 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, in amdgpu_ras_debugfs_set_ret_size()
1126 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control); in amdgpu_ras_debugfs_set_ret_size()
1134 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; in amdgpu_ras_debugfs_table_read() local
1139 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_debugfs_table_read()
1161 control->tbl_hdr.header, in amdgpu_ras_debugfs_table_read()
1162 control->tbl_hdr.version, in amdgpu_ras_debugfs_table_read()
1163 control->tbl_hdr.first_rec_offset, in amdgpu_ras_debugfs_table_read()
1164 control->tbl_hdr.tbl_size, in amdgpu_ras_debugfs_table_read()
1165 control->tbl_hdr.checksum); in amdgpu_ras_debugfs_table_read()
1191 data_len = amdgpu_ras_debugfs_table_size(control); in amdgpu_ras_debugfs_table_read()
1207 for ( ; size > 0 && s < control->ras_num_recs; s++) { in amdgpu_ras_debugfs_table_read()
1208 u32 ai = RAS_RI_TO_AI(control, s); in amdgpu_ras_debugfs_table_read()
1211 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1); in amdgpu_ras_debugfs_table_read()
1214 __decode_table_record_from_buf(control, &record, dare); in amdgpu_ras_debugfs_table_read()
1217 RAS_INDEX_TO_OFFSET(control, ai), in amdgpu_ras_debugfs_table_read()
1239 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_debugfs_table_read()
1249 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; in amdgpu_ras_debugfs_eeprom_table_read() local
1256 if (!ras || !control) { in amdgpu_ras_debugfs_eeprom_table_read()
1292 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control) in __verify_ras_table_checksum() argument
1294 struct amdgpu_device *adev = to_amdgpu_device(control); in __verify_ras_table_checksum()
1298 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) in __verify_ras_table_checksum()
1301 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in __verify_ras_table_checksum()
1304 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in __verify_ras_table_checksum()
1314 control->i2c_address + in __verify_ras_table_checksum()
1315 control->ras_header_offset, in __verify_ras_table_checksum()
1334 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control) in __read_table_ras_info() argument
1336 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; in __read_table_ras_info()
1337 struct amdgpu_device *adev = to_amdgpu_device(control); in __read_table_ras_info()
1353 control->i2c_address + control->ras_info_offset, in __read_table_ras_info()
1369 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_init() argument
1371 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_init()
1373 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_init()
1386 if (!__get_eeprom_i2c_addr(adev, control)) in amdgpu_ras_eeprom_init()
1389 control->ras_header_offset = RAS_HDR_START; in amdgpu_ras_eeprom_init()
1390 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START; in amdgpu_ras_eeprom_init()
1391 mutex_init(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_init()
1395 control->i2c_address + control->ras_header_offset, in amdgpu_ras_eeprom_init()
1408 return amdgpu_ras_eeprom_reset_table(control); in amdgpu_ras_eeprom_init()
1414 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr); in amdgpu_ras_eeprom_init()
1415 control->ras_record_offset = RAS_RECORD_START_V2_1; in amdgpu_ras_eeprom_init()
1416 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; in amdgpu_ras_eeprom_init()
1419 control->ras_num_recs = RAS_NUM_RECS(hdr); in amdgpu_ras_eeprom_init()
1420 control->ras_record_offset = RAS_RECORD_START; in amdgpu_ras_eeprom_init()
1421 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; in amdgpu_ras_eeprom_init()
1430 if (control->ras_num_recs > control->ras_max_record_count) { in amdgpu_ras_eeprom_init()
1433 control->ras_num_recs, control->ras_max_record_count); in amdgpu_ras_eeprom_init()
1437 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); in amdgpu_ras_eeprom_init()
1438 control->ras_num_mca_recs = 0; in amdgpu_ras_eeprom_init()
1439 control->ras_num_pa_recs = 0; in amdgpu_ras_eeprom_init()
1443 int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_check() argument
1445 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_check()
1446 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_check()
1457 if (!__get_eeprom_i2c_addr(adev, control)) in amdgpu_ras_eeprom_check()
1460 control->ras_num_bad_pages = control->ras_num_pa_recs + in amdgpu_ras_eeprom_check()
1461 control->ras_num_mca_recs * adev->umc.retire_unit; in amdgpu_ras_eeprom_check()
1466 control->ras_num_bad_pages); in amdgpu_ras_eeprom_check()
1469 res = __read_table_ras_info(control); in amdgpu_ras_eeprom_check()
1474 res = __verify_ras_table_checksum(control); in amdgpu_ras_eeprom_check()
1482 if (10 * control->ras_num_bad_pages >= 9 * ras->bad_page_cnt_threshold) in amdgpu_ras_eeprom_check()
1484 control->ras_num_bad_pages, in amdgpu_ras_eeprom_check()
1489 res = __read_table_ras_info(control); in amdgpu_ras_eeprom_check()
1494 res = __verify_ras_table_checksum(control); in amdgpu_ras_eeprom_check()
1501 if (ras->bad_page_cnt_threshold >= control->ras_num_bad_pages) { in amdgpu_ras_eeprom_check()
1511 control->ras_num_bad_pages, in amdgpu_ras_eeprom_check()
1513 res = amdgpu_ras_eeprom_correct_header_tag(control, in amdgpu_ras_eeprom_check()
1518 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_check()
1538 struct amdgpu_ras_eeprom_control *control; in amdgpu_ras_eeprom_check_and_recover() local
1543 control = &ras->eeprom_control; in amdgpu_ras_eeprom_check_and_recover()
1544 if (!control->is_eeprom_valid) in amdgpu_ras_eeprom_check_and_recover()
1546 res = __verify_ras_table_checksum(control); in amdgpu_ras_eeprom_check_and_recover()
1551 if (!amdgpu_ras_eeprom_reset_table(control)) in amdgpu_ras_eeprom_check_and_recover()
1553 if (!__verify_ras_table_checksum(control)) { in amdgpu_ras_eeprom_check_and_recover()
1558 control->is_eeprom_valid = false; in amdgpu_ras_eeprom_check_and_recover()