Lines Matching defs:amdgpu_rlc
274 struct amdgpu_rlc { struct
295 const struct amdgpu_rlc_funcs *funcs; argument
298 u32 save_and_restore_offset;
299 u32 clear_state_descriptor_offset;
300 u32 avail_scratch_ram_locations;
301 u32 reg_restore_list_size;
302 u32 reg_list_format_start;
303 u32 reg_list_format_separate_start;
304 u32 starting_offsets_start;
305 u32 reg_list_format_size_bytes;
306 u32 reg_list_size_bytes;
307 u32 reg_list_format_direct_reg_list_length;
308 u32 save_restore_list_cntl_size_bytes;
309 u32 save_restore_list_gpm_size_bytes;
310 u32 save_restore_list_srm_size_bytes;
311 u32 rlc_iram_ucode_size_bytes;
312 u32 rlc_dram_ucode_size_bytes;
313 u32 rlcp_ucode_size_bytes;
314 u32 rlcv_ucode_size_bytes;
315 u32 global_tap_delays_ucode_size_bytes;
316 u32 se0_tap_delays_ucode_size_bytes;
317 u32 se1_tap_delays_ucode_size_bytes;
318 u32 se2_tap_delays_ucode_size_bytes;
319 u32 se3_tap_delays_ucode_size_bytes;
321 u32 *register_list_format;
322 u32 *register_restore;
323 u8 *save_restore_list_cntl;
324 u8 *save_restore_list_gpm;
325 u8 *save_restore_list_srm;
326 u8 *rlc_iram_ucode;
350 struct amdgpu_rlcg_reg_access_ctrl reg_access_ctrl[AMDGPU_MAX_RLC_INSTANCES]; argument