Lines Matching refs:amdgpu_ring_write
466 amdgpu_ring_write(ring, ring->funcs->nop | in vpe_ring_insert_nop()
469 amdgpu_ring_write(ring, ring->funcs->nop); in vpe_ring_insert_nop()
494 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_PRED_EXE, 0) | in vpe_ring_emit_pred_exec()
496 amdgpu_ring_write(ring, exec_count & 0x1fff); in vpe_ring_emit_pred_exec()
507 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_INDIRECT, 0) | in vpe_ring_emit_ib()
511 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); in vpe_ring_emit_ib()
512 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in vpe_ring_emit_ib()
513 amdgpu_ring_write(ring, ib->length_dw); in vpe_ring_emit_ib()
514 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in vpe_ring_emit_ib()
515 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); in vpe_ring_emit_ib()
525 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0)); in vpe_ring_emit_fence()
528 amdgpu_ring_write(ring, lower_32_bits(addr)); in vpe_ring_emit_fence()
529 amdgpu_ring_write(ring, upper_32_bits(addr)); in vpe_ring_emit_fence()
530 amdgpu_ring_write(ring, i == 0 ? lower_32_bits(seq) : upper_32_bits(seq)); in vpe_ring_emit_fence()
536 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_TRAP, 0)); in vpe_ring_emit_fence()
537 amdgpu_ring_write(ring, 0); in vpe_ring_emit_fence()
550 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM, in vpe_ring_emit_pipeline_sync()
554 amdgpu_ring_write(ring, addr & 0xfffffffc); in vpe_ring_emit_pipeline_sync()
555 amdgpu_ring_write(ring, upper_32_bits(addr)); in vpe_ring_emit_pipeline_sync()
556 amdgpu_ring_write(ring, seq); /* reference */ in vpe_ring_emit_pipeline_sync()
557 amdgpu_ring_write(ring, 0xffffffff); /* mask */ in vpe_ring_emit_pipeline_sync()
558 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | in vpe_ring_emit_pipeline_sync()
566 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_REG_WRITE, 0)); in vpe_ring_emit_wreg()
567 amdgpu_ring_write(ring, reg << 2); in vpe_ring_emit_wreg()
568 amdgpu_ring_write(ring, val); in vpe_ring_emit_wreg()
576 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM, in vpe_ring_emit_reg_wait()
580 amdgpu_ring_write(ring, reg << 2); in vpe_ring_emit_reg_wait()
581 amdgpu_ring_write(ring, 0); in vpe_ring_emit_reg_wait()
582 amdgpu_ring_write(ring, val); /* reference */ in vpe_ring_emit_reg_wait()
583 amdgpu_ring_write(ring, mask); /* mask */ in vpe_ring_emit_reg_wait()
584 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) | in vpe_ring_emit_reg_wait()
599 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_COND_EXE, 0)); in vpe_ring_init_cond_exec()
600 amdgpu_ring_write(ring, lower_32_bits(addr)); in vpe_ring_init_cond_exec()
601 amdgpu_ring_write(ring, upper_32_bits(addr)); in vpe_ring_init_cond_exec()
602 amdgpu_ring_write(ring, 1); in vpe_ring_init_cond_exec()
604 amdgpu_ring_write(ring, 0); in vpe_ring_init_cond_exec()
772 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0)); in vpe_ring_test_ring()
773 amdgpu_ring_write(ring, lower_32_bits(wb_addr)); in vpe_ring_test_ring()
774 amdgpu_ring_write(ring, upper_32_bits(wb_addr)); in vpe_ring_test_ring()
775 amdgpu_ring_write(ring, test_pattern); in vpe_ring_test_ring()