Lines Matching refs:common_header
671 pcie_reg_state->common_header.structure_size = szbuf; in aqua_vanjaram_read_pcie_state()
672 pcie_reg_state->common_header.format_revision = 1; in aqua_vanjaram_read_pcie_state()
673 pcie_reg_state->common_header.content_revision = 0; in aqua_vanjaram_read_pcie_state()
674 pcie_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_PCIE; in aqua_vanjaram_read_pcie_state()
675 pcie_reg_state->common_header.num_instances = 1; in aqua_vanjaram_read_pcie_state()
677 return pcie_reg_state->common_header.structure_size; in aqua_vanjaram_read_pcie_state()
755 xgmi_reg_state->common_header.structure_size = szbuf; in aqua_vanjaram_read_xgmi_state()
756 xgmi_reg_state->common_header.format_revision = 1; in aqua_vanjaram_read_xgmi_state()
757 xgmi_reg_state->common_header.content_revision = 0; in aqua_vanjaram_read_xgmi_state()
758 xgmi_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_XGMI; in aqua_vanjaram_read_xgmi_state()
759 xgmi_reg_state->common_header.num_instances = max_xgmi_instances; in aqua_vanjaram_read_xgmi_state()
761 return xgmi_reg_state->common_header.structure_size; in aqua_vanjaram_read_xgmi_state()
828 wafl_reg_state->common_header.structure_size = szbuf; in aqua_vanjaram_read_wafl_state()
829 wafl_reg_state->common_header.format_revision = 1; in aqua_vanjaram_read_wafl_state()
830 wafl_reg_state->common_header.content_revision = 0; in aqua_vanjaram_read_wafl_state()
831 wafl_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_WAFL; in aqua_vanjaram_read_wafl_state()
832 wafl_reg_state->common_header.num_instances = max_wafl_instances; in aqua_vanjaram_read_wafl_state()
834 return wafl_reg_state->common_header.structure_size; in aqua_vanjaram_read_wafl_state()
947 usr_reg_state->common_header.structure_size = szbuf; in aqua_vanjaram_read_usr_state()
948 usr_reg_state->common_header.format_revision = 1; in aqua_vanjaram_read_usr_state()
949 usr_reg_state->common_header.content_revision = 0; in aqua_vanjaram_read_usr_state()
950 usr_reg_state->common_header.state_type = AMDGPU_REG_STATE_TYPE_USR; in aqua_vanjaram_read_usr_state()
951 usr_reg_state->common_header.num_instances = max_usr_instances; in aqua_vanjaram_read_usr_state()
953 return usr_reg_state->common_header.structure_size; in aqua_vanjaram_read_usr_state()