Lines Matching refs:ih
69 adev->irq.ih.enabled = true; in cik_ih_enable_interrupts()
91 adev->irq.ih.enabled = false; in cik_ih_disable_interrupts()
92 adev->irq.ih.rptr = 0; in cik_ih_disable_interrupts()
108 struct amdgpu_ih_ring *ih = &adev->irq.ih; in cik_ih_irq_init() local
126 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); in cik_ih_irq_init()
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cik_ih_irq_init()
136 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr)); in cik_ih_irq_init()
137 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(ih->wptr_addr) & 0xFF); in cik_ih_irq_init()
189 struct amdgpu_ih_ring *ih) in cik_ih_get_wptr() argument
193 wptr = le32_to_cpu(*ih->wptr_cpu); in cik_ih_get_wptr()
202 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cik_ih_get_wptr()
203 ih->rptr = (wptr + 16) & ih->ptr_mask; in cik_ih_get_wptr()
214 return (wptr & ih->ptr_mask); in cik_ih_get_wptr()
249 struct amdgpu_ih_ring *ih, in cik_ih_decode_iv() argument
253 u32 ring_index = ih->rptr >> 2; in cik_ih_decode_iv()
256 dw[0] = le32_to_cpu(ih->ring[ring_index + 0]); in cik_ih_decode_iv()
257 dw[1] = le32_to_cpu(ih->ring[ring_index + 1]); in cik_ih_decode_iv()
258 dw[2] = le32_to_cpu(ih->ring[ring_index + 2]); in cik_ih_decode_iv()
259 dw[3] = le32_to_cpu(ih->ring[ring_index + 3]); in cik_ih_decode_iv()
269 ih->rptr += 16; in cik_ih_decode_iv()
281 struct amdgpu_ih_ring *ih) in cik_ih_set_rptr() argument
283 WREG32(mmIH_RB_RPTR, ih->rptr); in cik_ih_set_rptr()
305 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false); in cik_ih_sw_init()