Lines Matching refs:amdgpu_ring_write
206 amdgpu_ring_write(ring, ring->funcs->nop | in cik_sdma_ring_insert_nop()
209 amdgpu_ring_write(ring, ring->funcs->nop); in cik_sdma_ring_insert_nop()
233 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); in cik_sdma_ring_emit_ib()
234 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_emit_ib()
235 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); in cik_sdma_ring_emit_ib()
236 amdgpu_ring_write(ring, ib->length_dw); in cik_sdma_ring_emit_ib()
258 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); in cik_sdma_ring_emit_hdp_flush()
259 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); in cik_sdma_ring_emit_hdp_flush()
260 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); in cik_sdma_ring_emit_hdp_flush()
261 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_ring_emit_hdp_flush()
262 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_ring_emit_hdp_flush()
263 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ in cik_sdma_ring_emit_hdp_flush()
283 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); in cik_sdma_ring_emit_fence()
284 amdgpu_ring_write(ring, lower_32_bits(addr)); in cik_sdma_ring_emit_fence()
285 amdgpu_ring_write(ring, upper_32_bits(addr)); in cik_sdma_ring_emit_fence()
286 amdgpu_ring_write(ring, lower_32_bits(seq)); in cik_sdma_ring_emit_fence()
291 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); in cik_sdma_ring_emit_fence()
292 amdgpu_ring_write(ring, lower_32_bits(addr)); in cik_sdma_ring_emit_fence()
293 amdgpu_ring_write(ring, upper_32_bits(addr)); in cik_sdma_ring_emit_fence()
294 amdgpu_ring_write(ring, upper_32_bits(seq)); in cik_sdma_ring_emit_fence()
298 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); in cik_sdma_ring_emit_fence()
621 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); in cik_sdma_ring_test_ring()
622 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
623 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
624 amdgpu_ring_write(ring, 1); /* number of DWs to follow */ in cik_sdma_ring_test_ring()
625 amdgpu_ring_write(ring, 0xDEADBEEF); in cik_sdma_ring_test_ring()
828 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, in cik_sdma_ring_emit_pipeline_sync()
832 amdgpu_ring_write(ring, addr & 0xfffffffc); in cik_sdma_ring_emit_pipeline_sync()
833 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); in cik_sdma_ring_emit_pipeline_sync()
834 amdgpu_ring_write(ring, seq); /* reference */ in cik_sdma_ring_emit_pipeline_sync()
835 amdgpu_ring_write(ring, 0xffffffff); /* mask */ in cik_sdma_ring_emit_pipeline_sync()
836 amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */ in cik_sdma_ring_emit_pipeline_sync()
857 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); in cik_sdma_ring_emit_vm_flush()
858 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); in cik_sdma_ring_emit_vm_flush()
859 amdgpu_ring_write(ring, 0); in cik_sdma_ring_emit_vm_flush()
860 amdgpu_ring_write(ring, 0); /* reference */ in cik_sdma_ring_emit_vm_flush()
861 amdgpu_ring_write(ring, 0); /* mask */ in cik_sdma_ring_emit_vm_flush()
862 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ in cik_sdma_ring_emit_vm_flush()
868 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); in cik_sdma_ring_emit_wreg()
869 amdgpu_ring_write(ring, reg); in cik_sdma_ring_emit_wreg()
870 amdgpu_ring_write(ring, val); in cik_sdma_ring_emit_wreg()