Lines Matching refs:amdgpu_crtc
237 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v10_0_page_flip() local
238 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; in dce_v10_0_page_flip()
242 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_page_flip()
245 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_page_flip()
247 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, in dce_v10_0_page_flip()
250 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v10_0_page_flip()
253 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_page_flip()
256 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v10_0_page_flip()
509 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v10_0_program_fmt() local
577 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_fmt()
595 struct amdgpu_crtc *amdgpu_crtc, in dce_v10_0_line_buffer_adjust() argument
599 u32 pipe_offset = amdgpu_crtc->crtc_id; in dce_v10_0_line_buffer_adjust()
608 if (amdgpu_crtc->base.enabled && mode) { in dce_v10_0_line_buffer_adjust()
628 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); in dce_v10_0_line_buffer_adjust()
630 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_line_buffer_adjust()
643 if (amdgpu_crtc->base.enabled && mode) { in dce_v10_0_line_buffer_adjust()
1027 struct amdgpu_crtc *amdgpu_crtc, in dce_v10_0_program_watermarks() argument
1030 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; in dce_v10_0_program_watermarks()
1037 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v10_0_program_watermarks()
1062 wm_high.vsc = amdgpu_crtc->vsc; in dce_v10_0_program_watermarks()
1064 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v10_0_program_watermarks()
1101 wm_low.vsc = amdgpu_crtc->vsc; in dce_v10_0_program_watermarks()
1103 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v10_0_program_watermarks()
1125 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1127 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1128 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1131 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1134 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1135 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1138 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1140 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v10_0_program_watermarks()
1143 amdgpu_crtc->line_time = line_time; in dce_v10_0_program_watermarks()
1144 amdgpu_crtc->wm_high = latency_watermark_a; in dce_v10_0_program_watermarks()
1145 amdgpu_crtc->wm_low = latency_watermark_b; in dce_v10_0_program_watermarks()
1147 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; in dce_v10_0_program_watermarks()
1543 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v10_0_audio_set_dto() local
1558 amdgpu_crtc->crtc_id); in dce_v10_0_audio_set_dto()
1590 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v10_0_afmt_setmode() local
1591 bpc = amdgpu_crtc->bpc; in dce_v10_0_afmt_setmode()
1821 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_vga_enable() local
1826 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; in dce_v10_0_vga_enable()
1828 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); in dce_v10_0_vga_enable()
1830 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); in dce_v10_0_vga_enable()
1835 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_grph_enable() local
1840 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); in dce_v10_0_grph_enable()
1842 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_grph_enable()
1849 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_do_set_base() local
2019 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_do_set_base()
2022 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_do_set_base()
2024 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2026 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2028 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2030 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2032 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v10_0_crtc_do_set_base()
2033 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v10_0_crtc_do_set_base()
2040 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_do_set_base()
2045 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_do_set_base()
2050 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2051 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2052 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2053 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2054 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); in dce_v10_0_crtc_do_set_base()
2055 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); in dce_v10_0_crtc_do_set_base()
2058 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); in dce_v10_0_crtc_do_set_base()
2062 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2067 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2071 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_do_set_base()
2075 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_do_set_base()
2097 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_set_interleave() local
2100 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); in dce_v10_0_set_interleave()
2105 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_set_interleave()
2110 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_load_lut() local
2117 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); in dce_v10_0_crtc_load_lut()
2119 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2122 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2124 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2126 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2128 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2130 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2132 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2135 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2137 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2139 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2140 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2141 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2143 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); in dce_v10_0_crtc_load_lut()
2144 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); in dce_v10_0_crtc_load_lut()
2145 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); in dce_v10_0_crtc_load_lut()
2147 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2148 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); in dce_v10_0_crtc_load_lut()
2150 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2155 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, in dce_v10_0_crtc_load_lut()
2161 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2165 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2167 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2170 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2172 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2175 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2177 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2180 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2183 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v10_0_crtc_load_lut()
2187 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2189 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
2245 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_pick_pll() local
2251 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { in dce_v10_0_pick_pll()
2283 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_lock_cursor() local
2286 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); in dce_v10_0_lock_cursor()
2291 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); in dce_v10_0_lock_cursor()
2296 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_hide_cursor() local
2300 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_hide_cursor()
2302 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_hide_cursor()
2307 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_show_cursor() local
2311 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v10_0_show_cursor()
2312 upper_32_bits(amdgpu_crtc->cursor_addr)); in dce_v10_0_show_cursor()
2313 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v10_0_show_cursor()
2314 lower_32_bits(amdgpu_crtc->cursor_addr)); in dce_v10_0_show_cursor()
2316 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_show_cursor()
2319 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_show_cursor()
2325 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_cursor_move_locked() local
2329 amdgpu_crtc->cursor_x = x; in dce_v10_0_cursor_move_locked()
2330 amdgpu_crtc->cursor_y = y; in dce_v10_0_cursor_move_locked()
2338 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); in dce_v10_0_cursor_move_locked()
2342 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); in dce_v10_0_cursor_move_locked()
2346 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); in dce_v10_0_cursor_move_locked()
2347 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); in dce_v10_0_cursor_move_locked()
2348 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, in dce_v10_0_cursor_move_locked()
2349 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); in dce_v10_0_cursor_move_locked()
2374 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_cursor_set2() local
2386 if ((width > amdgpu_crtc->max_cursor_width) || in dce_v10_0_crtc_cursor_set2()
2387 (height > amdgpu_crtc->max_cursor_height)) { in dce_v10_0_crtc_cursor_set2()
2394 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); in dce_v10_0_crtc_cursor_set2()
2413 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); in dce_v10_0_crtc_cursor_set2()
2417 if (width != amdgpu_crtc->cursor_width || in dce_v10_0_crtc_cursor_set2()
2418 height != amdgpu_crtc->cursor_height || in dce_v10_0_crtc_cursor_set2()
2419 hot_x != amdgpu_crtc->cursor_hot_x || in dce_v10_0_crtc_cursor_set2()
2420 hot_y != amdgpu_crtc->cursor_hot_y) { in dce_v10_0_crtc_cursor_set2()
2423 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; in dce_v10_0_crtc_cursor_set2()
2424 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; in dce_v10_0_crtc_cursor_set2()
2428 amdgpu_crtc->cursor_width = width; in dce_v10_0_crtc_cursor_set2()
2429 amdgpu_crtc->cursor_height = height; in dce_v10_0_crtc_cursor_set2()
2430 amdgpu_crtc->cursor_hot_x = hot_x; in dce_v10_0_crtc_cursor_set2()
2431 amdgpu_crtc->cursor_hot_y = hot_y; in dce_v10_0_crtc_cursor_set2()
2438 if (amdgpu_crtc->cursor_bo) { in dce_v10_0_crtc_cursor_set2()
2439 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); in dce_v10_0_crtc_cursor_set2()
2445 drm_gem_object_put(amdgpu_crtc->cursor_bo); in dce_v10_0_crtc_cursor_set2()
2448 amdgpu_crtc->cursor_bo = obj; in dce_v10_0_crtc_cursor_set2()
2454 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_cursor_reset() local
2456 if (amdgpu_crtc->cursor_bo) { in dce_v10_0_cursor_reset()
2459 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, in dce_v10_0_cursor_reset()
2460 amdgpu_crtc->cursor_y); in dce_v10_0_cursor_reset()
2479 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_destroy() local
2482 kfree(amdgpu_crtc); in dce_v10_0_crtc_destroy()
2502 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_dpms() local
2507 amdgpu_crtc->enabled = true; in dce_v10_0_crtc_dpms()
2514 amdgpu_crtc->crtc_id); in dce_v10_0_crtc_dpms()
2524 if (amdgpu_crtc->enabled) { in dce_v10_0_crtc_dpms()
2530 amdgpu_crtc->enabled = false; in dce_v10_0_crtc_dpms()
2553 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_disable() local
2581 i != amdgpu_crtc->crtc_id && in dce_v10_0_crtc_disable()
2582 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v10_0_crtc_disable()
2590 switch (amdgpu_crtc->pll_id) { in dce_v10_0_crtc_disable()
2595 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, in dce_v10_0_crtc_disable()
2602 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v10_0_crtc_disable()
2603 amdgpu_crtc->adjusted_clock = 0; in dce_v10_0_crtc_disable()
2604 amdgpu_crtc->encoder = NULL; in dce_v10_0_crtc_disable()
2605 amdgpu_crtc->connector = NULL; in dce_v10_0_crtc_disable()
2613 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_mode_set() local
2615 if (!amdgpu_crtc->adjusted_clock) in dce_v10_0_crtc_mode_set()
2625 amdgpu_crtc->hw_mode = *adjusted_mode; in dce_v10_0_crtc_mode_set()
2634 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v10_0_crtc_mode_fixup() local
2641 amdgpu_crtc->encoder = encoder; in dce_v10_0_crtc_mode_fixup()
2642 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); in dce_v10_0_crtc_mode_fixup()
2646 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { in dce_v10_0_crtc_mode_fixup()
2647 amdgpu_crtc->encoder = NULL; in dce_v10_0_crtc_mode_fixup()
2648 amdgpu_crtc->connector = NULL; in dce_v10_0_crtc_mode_fixup()
2656 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc); in dce_v10_0_crtc_mode_fixup()
2658 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && in dce_v10_0_crtc_mode_fixup()
2659 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) in dce_v10_0_crtc_mode_fixup()
2693 struct amdgpu_crtc *amdgpu_crtc; in dce_v10_0_panic_flush() local
2701 amdgpu_crtc = to_amdgpu_crtc(plane->crtc); in dce_v10_0_panic_flush()
2705 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_panic_flush()
2707 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v10_0_panic_flush()
2718 struct amdgpu_crtc *amdgpu_crtc; in dce_v10_0_crtc_init() local
2720 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + in dce_v10_0_crtc_init()
2722 if (amdgpu_crtc == NULL) in dce_v10_0_crtc_init()
2725 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v10_0_crtc_funcs); in dce_v10_0_crtc_init()
2727 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); in dce_v10_0_crtc_init()
2728 amdgpu_crtc->crtc_id = index; in dce_v10_0_crtc_init()
2729 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v10_0_crtc_init()
2731 amdgpu_crtc->max_cursor_width = 128; in dce_v10_0_crtc_init()
2732 amdgpu_crtc->max_cursor_height = 128; in dce_v10_0_crtc_init()
2733 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; in dce_v10_0_crtc_init()
2734 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; in dce_v10_0_crtc_init()
2736 switch (amdgpu_crtc->crtc_id) { in dce_v10_0_crtc_init()
2739 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2742 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2745 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2748 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2751 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2754 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; in dce_v10_0_crtc_init()
2758 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v10_0_crtc_init()
2759 amdgpu_crtc->adjusted_clock = 0; in dce_v10_0_crtc_init()
2760 amdgpu_crtc->encoder = NULL; in dce_v10_0_crtc_init()
2761 amdgpu_crtc->connector = NULL; in dce_v10_0_crtc_init()
2762 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs); in dce_v10_0_crtc_init()
2763 drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v10_0_drm_primary_plane_helper_funcs); in dce_v10_0_crtc_init()
3177 struct amdgpu_crtc *amdgpu_crtc; in dce_v10_0_pageflip_irq() local
3181 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v10_0_pageflip_irq()
3194 if (amdgpu_crtc == NULL) in dce_v10_0_pageflip_irq()
3198 works = amdgpu_crtc->pflip_works; in dce_v10_0_pageflip_irq()
3199 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { in dce_v10_0_pageflip_irq()
3202 amdgpu_crtc->pflip_status, in dce_v10_0_pageflip_irq()
3209 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; in dce_v10_0_pageflip_irq()
3210 amdgpu_crtc->pflip_works = NULL; in dce_v10_0_pageflip_irq()
3214 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); in dce_v10_0_pageflip_irq()
3218 drm_crtc_vblank_put(&amdgpu_crtc->base); in dce_v10_0_pageflip_irq()