Lines Matching refs:num_heads
705 u32 num_heads; /* number of active crtcs */ member
898 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v10_0_latency_watermark()
899 (wm->num_heads * cursor_line_pair_return_time); in dce_v10_0_latency_watermark()
905 if (wm->num_heads == 0) in dce_v10_0_latency_watermark()
919 b.full = dfixed_const(wm->num_heads); in dce_v10_0_latency_watermark()
954 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display()
974 (dce_v10_0_available_bandwidth(wm) / wm->num_heads)) in dce_v10_0_average_bandwidth_vs_available_bandwidth()
1028 u32 lb_size, u32 num_heads) in dce_v10_0_program_watermarks() argument
1037 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v10_0_program_watermarks()
1069 wm_high.num_heads = num_heads; in dce_v10_0_program_watermarks()
1108 wm_low.num_heads = num_heads; in dce_v10_0_program_watermarks()
1161 u32 num_heads = 0, lb_size; in dce_v10_0_bandwidth_update() local
1168 num_heads++; in dce_v10_0_bandwidth_update()
1174 lb_size, num_heads); in dce_v10_0_bandwidth_update()