Lines Matching refs:afmt
1249 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_afmt_audio_select_pin()
1252 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_audio_select_pin()
1253 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); in dce_v11_0_afmt_audio_select_pin()
1254 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_audio_select_pin()
1270 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_audio_write_latency_fields()
1300 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v11_0_audio_write_latency_fields()
1317 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_audio_write_speaker_allocation()
1341 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v11_0_audio_write_speaker_allocation()
1354 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v11_0_audio_write_speaker_allocation()
1387 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v11_0_audio_write_sad_regs()
1440 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); in dce_v11_0_audio_write_sad_regs()
1540 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1542 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1543 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1545 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1547 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1549 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1550 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1552 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1554 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1556 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1557 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1559 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
1576 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1578 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1580 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1582 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, in dce_v11_0_afmt_update_avi_infoframe()
1597 if (!dig || !dig->afmt) in dce_v11_0_audio_set_dto()
1630 if (!dig || !dig->afmt) in dce_v11_0_afmt_setmode()
1634 if (!dig->afmt->enabled) in dce_v11_0_afmt_setmode()
1644 dig->afmt->pin = dce_v11_0_audio_get_pin(adev); in dce_v11_0_afmt_setmode()
1645 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); in dce_v11_0_afmt_setmode()
1649 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1651 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ in dce_v11_0_afmt_setmode()
1653 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); in dce_v11_0_afmt_setmode()
1655 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1680 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1682 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1686 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1688 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1693 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1695 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1698 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1700 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1703 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1705 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ in dce_v11_0_afmt_setmode()
1707 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1712 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1714 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1717 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1719 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1728 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1732 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1734 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1736 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1738 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1740 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1747 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1751 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, in dce_v11_0_afmt_setmode()
1772 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1777 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1779 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1781 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1783 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v11_0_afmt_setmode()
1786 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v11_0_afmt_setmode()
1788 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); in dce_v11_0_afmt_setmode()
1789 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); in dce_v11_0_afmt_setmode()
1790 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); in dce_v11_0_afmt_setmode()
1791 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); in dce_v11_0_afmt_setmode()
1794 dce_v11_0_audio_enable(adev, dig->afmt->pin, true); in dce_v11_0_afmt_setmode()
1804 if (!dig || !dig->afmt) in dce_v11_0_afmt_enable()
1808 if (enable && dig->afmt->enabled) in dce_v11_0_afmt_enable()
1810 if (!enable && !dig->afmt->enabled) in dce_v11_0_afmt_enable()
1813 if (!enable && dig->afmt->pin) { in dce_v11_0_afmt_enable()
1814 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); in dce_v11_0_afmt_enable()
1815 dig->afmt->pin = NULL; in dce_v11_0_afmt_enable()
1818 dig->afmt->enabled = enable; in dce_v11_0_afmt_enable()
1821 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); in dce_v11_0_afmt_enable()
1829 adev->mode_info.afmt[i] = NULL; in dce_v11_0_afmt_init()
1833 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); in dce_v11_0_afmt_init()
1834 if (adev->mode_info.afmt[i]) { in dce_v11_0_afmt_init()
1835 adev->mode_info.afmt[i]->offset = dig_offsets[i]; in dce_v11_0_afmt_init()
1836 adev->mode_info.afmt[i]->id = i; in dce_v11_0_afmt_init()
1840 kfree(adev->mode_info.afmt[j]); in dce_v11_0_afmt_init()
1841 adev->mode_info.afmt[j] = NULL; in dce_v11_0_afmt_init()
1854 kfree(adev->mode_info.afmt[i]); in dce_v11_0_afmt_fini()
1855 adev->mode_info.afmt[i] = NULL; in dce_v11_0_afmt_fini()
3525 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; in dce_v11_0_encoder_prepare()