Lines Matching refs:amdgpu_crtc
261 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v11_0_page_flip() local
262 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; in dce_v11_0_page_flip()
266 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_page_flip()
269 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_page_flip()
271 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, in dce_v11_0_page_flip()
274 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_page_flip()
277 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_page_flip()
280 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v11_0_page_flip()
541 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v11_0_program_fmt() local
609 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_fmt()
627 struct amdgpu_crtc *amdgpu_crtc, in dce_v11_0_line_buffer_adjust() argument
631 u32 pipe_offset = amdgpu_crtc->crtc_id; in dce_v11_0_line_buffer_adjust()
640 if (amdgpu_crtc->base.enabled && mode) { in dce_v11_0_line_buffer_adjust()
660 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); in dce_v11_0_line_buffer_adjust()
662 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_line_buffer_adjust()
675 if (amdgpu_crtc->base.enabled && mode) { in dce_v11_0_line_buffer_adjust()
1059 struct amdgpu_crtc *amdgpu_crtc, in dce_v11_0_program_watermarks() argument
1062 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; in dce_v11_0_program_watermarks()
1069 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v11_0_program_watermarks()
1094 wm_high.vsc = amdgpu_crtc->vsc; in dce_v11_0_program_watermarks()
1096 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v11_0_program_watermarks()
1133 wm_low.vsc = amdgpu_crtc->vsc; in dce_v11_0_program_watermarks()
1135 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v11_0_program_watermarks()
1157 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1159 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1160 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1163 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1166 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1167 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1170 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1172 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); in dce_v11_0_program_watermarks()
1175 amdgpu_crtc->line_time = line_time; in dce_v11_0_program_watermarks()
1176 amdgpu_crtc->wm_high = latency_watermark_a; in dce_v11_0_program_watermarks()
1177 amdgpu_crtc->wm_low = latency_watermark_b; in dce_v11_0_program_watermarks()
1179 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; in dce_v11_0_program_watermarks()
1592 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v11_0_audio_set_dto() local
1607 amdgpu_crtc->crtc_id); in dce_v11_0_audio_set_dto()
1639 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v11_0_afmt_setmode() local
1640 bpc = amdgpu_crtc->bpc; in dce_v11_0_afmt_setmode()
1871 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v11_0_vga_enable() local
1876 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; in dce_v11_0_vga_enable()
1878 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); in dce_v11_0_vga_enable()
1880 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); in dce_v11_0_vga_enable()
1885 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v11_0_grph_enable() local
1890 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); in dce_v11_0_grph_enable()
1892 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_grph_enable()
1899 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v11_0_crtc_do_set_base() local
2069 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_do_set_base()
2072 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_do_set_base()
2074 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2076 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2078 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2080 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2082 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v11_0_crtc_do_set_base()
2083 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v11_0_crtc_do_set_base()
2090 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_do_set_base()
2095 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_do_set_base()
2100 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2101 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2102 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2103 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2104 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); in dce_v11_0_crtc_do_set_base()
2105 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); in dce_v11_0_crtc_do_set_base()
2108 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); in dce_v11_0_crtc_do_set_base()
2112 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2117 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2121 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_do_set_base()
2125 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
2147 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v11_0_set_interleave() local
2150 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); in dce_v11_0_set_interleave()
2155 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_set_interleave()
2160 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v11_0_crtc_load_lut() local
2167 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); in dce_v11_0_crtc_load_lut()
2169 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2171 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2173 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2175 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2177 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2179 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2181 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2183 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2184 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2185 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2187 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); in dce_v11_0_crtc_load_lut()
2188 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); in dce_v11_0_crtc_load_lut()
2189 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); in dce_v11_0_crtc_load_lut()
2191 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2192 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); in dce_v11_0_crtc_load_lut()
2194 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2199 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, in dce_v11_0_crtc_load_lut()
2205 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2209 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2211 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2213 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2215 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2217 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2219 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2221 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2224 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_load_lut()
2228 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2230 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
2286 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v11_0_pick_pll() local
2297 to_amdgpu_encoder(amdgpu_crtc->encoder); in dce_v11_0_pick_pll()
2300 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) in dce_v11_0_pick_pll()
2325 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { in dce_v11_0_pick_pll()
2367 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v11_0_lock_cursor() local
2370 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); in dce_v11_0_lock_cursor()
2375 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); in dce_v11_0_lock_cursor()
2380 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v11_0_hide_cursor() local
2384 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_hide_cursor()
2386 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_hide_cursor()
2391 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v11_0_show_cursor() local
2395 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v11_0_show_cursor()
2396 upper_32_bits(amdgpu_crtc->cursor_addr)); in dce_v11_0_show_cursor()
2397 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v11_0_show_cursor()
2398 lower_32_bits(amdgpu_crtc->cursor_addr)); in dce_v11_0_show_cursor()
2400 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_show_cursor()
2403 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_show_cursor()
2409 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v11_0_cursor_move_locked() local
2413 amdgpu_crtc->cursor_x = x; in dce_v11_0_cursor_move_locked()
2414 amdgpu_crtc->cursor_y = y; in dce_v11_0_cursor_move_locked()
2422 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); in dce_v11_0_cursor_move_locked()
2426 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); in dce_v11_0_cursor_move_locked()
2430 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); in dce_v11_0_cursor_move_locked()
2431 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); in dce_v11_0_cursor_move_locked()
2432 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, in dce_v11_0_cursor_move_locked()
2433 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); in dce_v11_0_cursor_move_locked()
2458 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v11_0_crtc_cursor_set2() local
2470 if ((width > amdgpu_crtc->max_cursor_width) || in dce_v11_0_crtc_cursor_set2()
2471 (height > amdgpu_crtc->max_cursor_height)) { in dce_v11_0_crtc_cursor_set2()
2478 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); in dce_v11_0_crtc_cursor_set2()
2497 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); in dce_v11_0_crtc_cursor_set2()
2501 if (width != amdgpu_crtc->cursor_width || in dce_v11_0_crtc_cursor_set2()
2502 height != amdgpu_crtc->cursor_height || in dce_v11_0_crtc_cursor_set2()
2503 hot_x != amdgpu_crtc->cursor_hot_x || in dce_v11_0_crtc_cursor_set2()
2504 hot_y != amdgpu_crtc->cursor_hot_y) { in dce_v11_0_crtc_cursor_set2()
2507 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; in dce_v11_0_crtc_cursor_set2()
2508 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; in dce_v11_0_crtc_cursor_set2()
2512 amdgpu_crtc->cursor_width = width; in dce_v11_0_crtc_cursor_set2()
2513 amdgpu_crtc->cursor_height = height; in dce_v11_0_crtc_cursor_set2()
2514 amdgpu_crtc->cursor_hot_x = hot_x; in dce_v11_0_crtc_cursor_set2()
2515 amdgpu_crtc->cursor_hot_y = hot_y; in dce_v11_0_crtc_cursor_set2()
2522 if (amdgpu_crtc->cursor_bo) { in dce_v11_0_crtc_cursor_set2()
2523 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); in dce_v11_0_crtc_cursor_set2()
2529 drm_gem_object_put(amdgpu_crtc->cursor_bo); in dce_v11_0_crtc_cursor_set2()
2532 amdgpu_crtc->cursor_bo = obj; in dce_v11_0_crtc_cursor_set2()
2538 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v11_0_cursor_reset() local
2540 if (amdgpu_crtc->cursor_bo) { in dce_v11_0_cursor_reset()
2543 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, in dce_v11_0_cursor_reset()
2544 amdgpu_crtc->cursor_y); in dce_v11_0_cursor_reset()
2563 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v11_0_crtc_destroy() local
2566 kfree(amdgpu_crtc); in dce_v11_0_crtc_destroy()
2586 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v11_0_crtc_dpms() local
2591 amdgpu_crtc->enabled = true; in dce_v11_0_crtc_dpms()
2598 amdgpu_crtc->crtc_id); in dce_v11_0_crtc_dpms()
2608 if (amdgpu_crtc->enabled) { in dce_v11_0_crtc_dpms()
2614 amdgpu_crtc->enabled = false; in dce_v11_0_crtc_dpms()
2637 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v11_0_crtc_disable() local
2665 i != amdgpu_crtc->crtc_id && in dce_v11_0_crtc_disable()
2666 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v11_0_crtc_disable()
2674 switch (amdgpu_crtc->pll_id) { in dce_v11_0_crtc_disable()
2679 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, in dce_v11_0_crtc_disable()
2689 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id, in dce_v11_0_crtc_disable()
2696 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v11_0_crtc_disable()
2697 amdgpu_crtc->adjusted_clock = 0; in dce_v11_0_crtc_disable()
2698 amdgpu_crtc->encoder = NULL; in dce_v11_0_crtc_disable()
2699 amdgpu_crtc->connector = NULL; in dce_v11_0_crtc_disable()
2707 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v11_0_crtc_mode_set() local
2711 if (!amdgpu_crtc->adjusted_clock) in dce_v11_0_crtc_mode_set()
2719 to_amdgpu_encoder(amdgpu_crtc->encoder); in dce_v11_0_crtc_mode_set()
2721 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); in dce_v11_0_crtc_mode_set()
2724 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, in dce_v11_0_crtc_mode_set()
2725 amdgpu_crtc->pll_id, in dce_v11_0_crtc_mode_set()
2728 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); in dce_v11_0_crtc_mode_set()
2738 amdgpu_crtc->hw_mode = *adjusted_mode; in dce_v11_0_crtc_mode_set()
2747 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v11_0_crtc_mode_fixup() local
2754 amdgpu_crtc->encoder = encoder; in dce_v11_0_crtc_mode_fixup()
2755 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); in dce_v11_0_crtc_mode_fixup()
2759 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { in dce_v11_0_crtc_mode_fixup()
2760 amdgpu_crtc->encoder = NULL; in dce_v11_0_crtc_mode_fixup()
2761 amdgpu_crtc->connector = NULL; in dce_v11_0_crtc_mode_fixup()
2769 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc); in dce_v11_0_crtc_mode_fixup()
2771 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && in dce_v11_0_crtc_mode_fixup()
2772 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) in dce_v11_0_crtc_mode_fixup()
2806 struct amdgpu_crtc *amdgpu_crtc; in dce_v11_0_panic_flush() local
2814 amdgpu_crtc = to_amdgpu_crtc(plane->crtc); in dce_v11_0_panic_flush()
2818 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_panic_flush()
2820 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v11_0_panic_flush()
2831 struct amdgpu_crtc *amdgpu_crtc; in dce_v11_0_crtc_init() local
2833 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + in dce_v11_0_crtc_init()
2835 if (amdgpu_crtc == NULL) in dce_v11_0_crtc_init()
2838 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v11_0_crtc_funcs); in dce_v11_0_crtc_init()
2840 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); in dce_v11_0_crtc_init()
2841 amdgpu_crtc->crtc_id = index; in dce_v11_0_crtc_init()
2842 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v11_0_crtc_init()
2844 amdgpu_crtc->max_cursor_width = 128; in dce_v11_0_crtc_init()
2845 amdgpu_crtc->max_cursor_height = 128; in dce_v11_0_crtc_init()
2846 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; in dce_v11_0_crtc_init()
2847 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; in dce_v11_0_crtc_init()
2849 switch (amdgpu_crtc->crtc_id) { in dce_v11_0_crtc_init()
2852 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2855 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2858 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2861 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2864 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2867 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; in dce_v11_0_crtc_init()
2871 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v11_0_crtc_init()
2872 amdgpu_crtc->adjusted_clock = 0; in dce_v11_0_crtc_init()
2873 amdgpu_crtc->encoder = NULL; in dce_v11_0_crtc_init()
2874 amdgpu_crtc->connector = NULL; in dce_v11_0_crtc_init()
2875 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); in dce_v11_0_crtc_init()
2876 drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v11_0_drm_primary_plane_helper_funcs); in dce_v11_0_crtc_init()
3308 struct amdgpu_crtc *amdgpu_crtc; in dce_v11_0_pageflip_irq() local
3312 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v11_0_pageflip_irq()
3325 if(amdgpu_crtc == NULL) in dce_v11_0_pageflip_irq()
3329 works = amdgpu_crtc->pflip_works; in dce_v11_0_pageflip_irq()
3330 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ in dce_v11_0_pageflip_irq()
3333 amdgpu_crtc->pflip_status, in dce_v11_0_pageflip_irq()
3340 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; in dce_v11_0_pageflip_irq()
3341 amdgpu_crtc->pflip_works = NULL; in dce_v11_0_pageflip_irq()
3345 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); in dce_v11_0_pageflip_irq()
3349 drm_crtc_vblank_put(&amdgpu_crtc->base); in dce_v11_0_pageflip_irq()