Lines Matching refs:amdgpu_crtc
204 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v6_0_page_flip() local
205 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; in dce_v6_0_page_flip()
208 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? in dce_v6_0_page_flip()
211 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
214 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
217 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
220 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v6_0_page_flip()
462 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v6_0_program_fmt() local
509 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_fmt()
880 struct amdgpu_crtc *amdgpu_crtc, in dce_v6_0_program_watermarks() argument
883 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; in dce_v6_0_program_watermarks()
895 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v6_0_program_watermarks()
924 wm_high.vsc = amdgpu_crtc->vsc; in dce_v6_0_program_watermarks()
926 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v6_0_program_watermarks()
951 wm_low.vsc = amdgpu_crtc->vsc; in dce_v6_0_program_watermarks()
953 if (amdgpu_crtc->rmx_type != RMX_OFF) in dce_v6_0_program_watermarks()
989 c.full = dfixed_mul(c, amdgpu_crtc->hsc); in dce_v6_0_program_watermarks()
1001 c.full = dfixed_mul(c, amdgpu_crtc->hsc); in dce_v6_0_program_watermarks()
1012 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); in dce_v6_0_program_watermarks()
1016 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_watermarks()
1017 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_program_watermarks()
1021 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); in dce_v6_0_program_watermarks()
1024 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_watermarks()
1025 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_program_watermarks()
1029 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); in dce_v6_0_program_watermarks()
1032 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); in dce_v6_0_program_watermarks()
1033 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); in dce_v6_0_program_watermarks()
1036 amdgpu_crtc->line_time = line_time; in dce_v6_0_program_watermarks()
1037 amdgpu_crtc->wm_high = latency_watermark_a; in dce_v6_0_program_watermarks()
1040 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; in dce_v6_0_program_watermarks()
1059 struct amdgpu_crtc *amdgpu_crtc, in dce_v6_0_line_buffer_adjust() argument
1064 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; in dce_v6_0_line_buffer_adjust()
1078 if (amdgpu_crtc->base.enabled && mode) { in dce_v6_0_line_buffer_adjust()
1091 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, in dce_v6_0_line_buffer_adjust()
1103 if (amdgpu_crtc->base.enabled && mode) { in dce_v6_0_line_buffer_adjust()
1568 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v6_0_audio_set_dto() local
1580 DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id); in dce_v6_0_audio_set_dto()
1758 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); in dce_v6_0_afmt_setmode() local
1759 bpc = amdgpu_crtc->bpc; in dce_v6_0_afmt_setmode()
1865 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_vga_enable() local
1870 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; in dce_v6_0_vga_enable()
1871 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0)); in dce_v6_0_vga_enable()
1876 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_grph_enable() local
1880 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); in dce_v6_0_grph_enable()
1887 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_crtc_do_set_base() local
2040 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2042 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2044 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2046 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2048 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2050 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v6_0_crtc_do_set_base()
2051 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v6_0_crtc_do_set_base()
2058 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2065 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2066 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2067 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2068 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2069 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); in dce_v6_0_crtc_do_set_base()
2070 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); in dce_v6_0_crtc_do_set_base()
2073 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); in dce_v6_0_crtc_do_set_base()
2077 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2081 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2086 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2090 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2113 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_set_interleave() local
2116 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, in dce_v6_0_set_interleave()
2119 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_set_interleave()
2124 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_crtc_load_lut() local
2130 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); in dce_v6_0_crtc_load_lut()
2132 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2135 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2137 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2139 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2143 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2145 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2146 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2147 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2149 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2150 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2151 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2153 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2154 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); in dce_v6_0_crtc_load_lut()
2156 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2161 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2167 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2172 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2175 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2178 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2182 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2224 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_pick_pll() local
2230 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { in dce_v6_0_pick_pll()
2256 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_lock_cursor() local
2259 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); in dce_v6_0_lock_cursor()
2264 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); in dce_v6_0_lock_cursor()
2269 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_hide_cursor() local
2272 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_hide_cursor()
2279 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_show_cursor() local
2282 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2283 upper_32_bits(amdgpu_crtc->cursor_addr)); in dce_v6_0_show_cursor()
2284 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2285 lower_32_bits(amdgpu_crtc->cursor_addr)); in dce_v6_0_show_cursor()
2287 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2296 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_cursor_move_locked() local
2300 int w = amdgpu_crtc->cursor_width; in dce_v6_0_cursor_move_locked()
2302 amdgpu_crtc->cursor_x = x; in dce_v6_0_cursor_move_locked()
2303 amdgpu_crtc->cursor_y = y; in dce_v6_0_cursor_move_locked()
2311 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); in dce_v6_0_cursor_move_locked()
2315 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); in dce_v6_0_cursor_move_locked()
2319 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); in dce_v6_0_cursor_move_locked()
2320 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); in dce_v6_0_cursor_move_locked()
2321 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, in dce_v6_0_cursor_move_locked()
2322 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); in dce_v6_0_cursor_move_locked()
2347 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_crtc_cursor_set2() local
2359 if ((width > amdgpu_crtc->max_cursor_width) || in dce_v6_0_crtc_cursor_set2()
2360 (height > amdgpu_crtc->max_cursor_height)) { in dce_v6_0_crtc_cursor_set2()
2367 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); in dce_v6_0_crtc_cursor_set2()
2386 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); in dce_v6_0_crtc_cursor_set2()
2390 if (width != amdgpu_crtc->cursor_width || in dce_v6_0_crtc_cursor_set2()
2391 height != amdgpu_crtc->cursor_height || in dce_v6_0_crtc_cursor_set2()
2392 hot_x != amdgpu_crtc->cursor_hot_x || in dce_v6_0_crtc_cursor_set2()
2393 hot_y != amdgpu_crtc->cursor_hot_y) { in dce_v6_0_crtc_cursor_set2()
2396 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; in dce_v6_0_crtc_cursor_set2()
2397 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; in dce_v6_0_crtc_cursor_set2()
2401 amdgpu_crtc->cursor_width = width; in dce_v6_0_crtc_cursor_set2()
2402 amdgpu_crtc->cursor_height = height; in dce_v6_0_crtc_cursor_set2()
2403 amdgpu_crtc->cursor_hot_x = hot_x; in dce_v6_0_crtc_cursor_set2()
2404 amdgpu_crtc->cursor_hot_y = hot_y; in dce_v6_0_crtc_cursor_set2()
2411 if (amdgpu_crtc->cursor_bo) { in dce_v6_0_crtc_cursor_set2()
2412 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); in dce_v6_0_crtc_cursor_set2()
2418 drm_gem_object_put(amdgpu_crtc->cursor_bo); in dce_v6_0_crtc_cursor_set2()
2421 amdgpu_crtc->cursor_bo = obj; in dce_v6_0_crtc_cursor_set2()
2427 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_cursor_reset() local
2429 if (amdgpu_crtc->cursor_bo) { in dce_v6_0_cursor_reset()
2432 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, in dce_v6_0_cursor_reset()
2433 amdgpu_crtc->cursor_y); in dce_v6_0_cursor_reset()
2451 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_crtc_destroy() local
2454 kfree(amdgpu_crtc); in dce_v6_0_crtc_destroy()
2474 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_crtc_dpms() local
2479 amdgpu_crtc->enabled = true; in dce_v6_0_crtc_dpms()
2484 amdgpu_crtc->crtc_id); in dce_v6_0_crtc_dpms()
2494 if (amdgpu_crtc->enabled) in dce_v6_0_crtc_dpms()
2497 amdgpu_crtc->enabled = false; in dce_v6_0_crtc_dpms()
2521 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_crtc_disable() local
2549 i != amdgpu_crtc->crtc_id && in dce_v6_0_crtc_disable()
2550 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { in dce_v6_0_crtc_disable()
2558 switch (amdgpu_crtc->pll_id) { in dce_v6_0_crtc_disable()
2562 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, in dce_v6_0_crtc_disable()
2569 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v6_0_crtc_disable()
2570 amdgpu_crtc->adjusted_clock = 0; in dce_v6_0_crtc_disable()
2571 amdgpu_crtc->encoder = NULL; in dce_v6_0_crtc_disable()
2572 amdgpu_crtc->connector = NULL; in dce_v6_0_crtc_disable()
2580 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_crtc_mode_set() local
2582 if (!amdgpu_crtc->adjusted_clock) in dce_v6_0_crtc_mode_set()
2592 amdgpu_crtc->hw_mode = *adjusted_mode; in dce_v6_0_crtc_mode_set()
2601 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); in dce_v6_0_crtc_mode_fixup() local
2608 amdgpu_crtc->encoder = encoder; in dce_v6_0_crtc_mode_fixup()
2609 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); in dce_v6_0_crtc_mode_fixup()
2613 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { in dce_v6_0_crtc_mode_fixup()
2614 amdgpu_crtc->encoder = NULL; in dce_v6_0_crtc_mode_fixup()
2615 amdgpu_crtc->connector = NULL; in dce_v6_0_crtc_mode_fixup()
2623 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc); in dce_v6_0_crtc_mode_fixup()
2625 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && in dce_v6_0_crtc_mode_fixup()
2626 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) in dce_v6_0_crtc_mode_fixup()
2660 struct amdgpu_crtc *amdgpu_crtc; in dce_v6_0_panic_flush() local
2668 amdgpu_crtc = to_amdgpu_crtc(plane->crtc); in dce_v6_0_panic_flush()
2672 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v6_0_panic_flush()
2674 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v6_0_panic_flush()
2685 struct amdgpu_crtc *amdgpu_crtc; in dce_v6_0_crtc_init() local
2687 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + in dce_v6_0_crtc_init()
2689 if (amdgpu_crtc == NULL) in dce_v6_0_crtc_init()
2692 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v6_0_crtc_funcs); in dce_v6_0_crtc_init()
2694 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); in dce_v6_0_crtc_init()
2695 amdgpu_crtc->crtc_id = index; in dce_v6_0_crtc_init()
2696 adev->mode_info.crtcs[index] = amdgpu_crtc; in dce_v6_0_crtc_init()
2698 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH; in dce_v6_0_crtc_init()
2699 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT; in dce_v6_0_crtc_init()
2700 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; in dce_v6_0_crtc_init()
2701 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; in dce_v6_0_crtc_init()
2703 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; in dce_v6_0_crtc_init()
2705 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; in dce_v6_0_crtc_init()
2706 amdgpu_crtc->adjusted_clock = 0; in dce_v6_0_crtc_init()
2707 amdgpu_crtc->encoder = NULL; in dce_v6_0_crtc_init()
2708 amdgpu_crtc->connector = NULL; in dce_v6_0_crtc_init()
2709 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); in dce_v6_0_crtc_init()
2710 drm_plane_helper_add(amdgpu_crtc->base.primary, &dce_v6_0_drm_primary_plane_helper_funcs); in dce_v6_0_crtc_init()
3152 struct amdgpu_crtc *amdgpu_crtc; in dce_v6_0_pageflip_irq() local
3156 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; in dce_v6_0_pageflip_irq()
3169 if (amdgpu_crtc == NULL) in dce_v6_0_pageflip_irq()
3173 works = amdgpu_crtc->pflip_works; in dce_v6_0_pageflip_irq()
3174 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { in dce_v6_0_pageflip_irq()
3177 amdgpu_crtc->pflip_status, in dce_v6_0_pageflip_irq()
3184 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; in dce_v6_0_pageflip_irq()
3185 amdgpu_crtc->pflip_works = NULL; in dce_v6_0_pageflip_irq()
3189 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); in dce_v6_0_pageflip_irq()
3193 drm_crtc_vblank_put(&amdgpu_crtc->base); in dce_v6_0_pageflip_irq()