Lines Matching refs:crtc_offset
208 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? in dce_v6_0_page_flip()
211 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
214 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
217 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_page_flip()
220 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); in dce_v6_0_page_flip()
509 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_fmt()
1012 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); in dce_v6_0_program_watermarks()
1016 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_watermarks()
1017 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_program_watermarks()
1021 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); in dce_v6_0_program_watermarks()
1024 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); in dce_v6_0_program_watermarks()
1025 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_program_watermarks()
1029 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); in dce_v6_0_program_watermarks()
1032 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); in dce_v6_0_program_watermarks()
1033 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); in dce_v6_0_program_watermarks()
1091 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, in dce_v6_0_line_buffer_adjust()
1880 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); in dce_v6_0_grph_enable()
2040 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2042 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2044 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2046 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2048 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2050 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v6_0_crtc_do_set_base()
2051 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); in dce_v6_0_crtc_do_set_base()
2058 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2065 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2066 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2067 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2068 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2069 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); in dce_v6_0_crtc_do_set_base()
2070 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); in dce_v6_0_crtc_do_set_base()
2073 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); in dce_v6_0_crtc_do_set_base()
2077 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2081 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2086 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_do_set_base()
2090 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_do_set_base()
2116 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, in dce_v6_0_set_interleave()
2119 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_set_interleave()
2132 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2135 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2137 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2139 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2143 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2145 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2146 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2147 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2149 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2150 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2151 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); in dce_v6_0_crtc_load_lut()
2153 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2154 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); in dce_v6_0_crtc_load_lut()
2156 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2161 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2167 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2172 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2175 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2178 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_crtc_load_lut()
2182 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); in dce_v6_0_crtc_load_lut()
2259 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); in dce_v6_0_lock_cursor()
2264 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); in dce_v6_0_lock_cursor()
2272 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_hide_cursor()
2282 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2284 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2287 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_show_cursor()
2319 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); in dce_v6_0_cursor_move_locked()
2320 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); in dce_v6_0_cursor_move_locked()
2321 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, in dce_v6_0_cursor_move_locked()
2672 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v6_0_panic_flush()
2674 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v6_0_panic_flush()
2703 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; in dce_v6_0_crtc_init()