Lines Matching refs:fb_format
1894 uint32_t fb_format, fb_pitch_pixels, pipe_config; in dce_v6_0_crtc_do_set_base() local
1935 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | in dce_v6_0_crtc_do_set_base()
1940 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | in dce_v6_0_crtc_do_set_base()
1948 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | in dce_v6_0_crtc_do_set_base()
1956 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | in dce_v6_0_crtc_do_set_base()
1963 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | in dce_v6_0_crtc_do_set_base()
1971 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | in dce_v6_0_crtc_do_set_base()
1979 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | in dce_v6_0_crtc_do_set_base()
1989 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | in dce_v6_0_crtc_do_set_base()
1999 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | in dce_v6_0_crtc_do_set_base()
2022 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT); in dce_v6_0_crtc_do_set_base()
2023 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); in dce_v6_0_crtc_do_set_base()
2024 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT); in dce_v6_0_crtc_do_set_base()
2025 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT); in dce_v6_0_crtc_do_set_base()
2026 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT); in dce_v6_0_crtc_do_set_base()
2027 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT); in dce_v6_0_crtc_do_set_base()
2029 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); in dce_v6_0_crtc_do_set_base()
2033 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT); in dce_v6_0_crtc_do_set_base()
2050 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v6_0_crtc_do_set_base()
2662 uint32_t fb_format; in dce_v6_0_panic_flush() local
2672 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v6_0_panic_flush()
2673 fb_format &= ~GRPH_CONTROL__GRPH_ARRAY_MODE_MASK; in dce_v6_0_panic_flush()
2674 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v6_0_panic_flush()