Lines Matching refs:num_heads
558 u32 num_heads; /* number of active crtcs */ member
751 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + in dce_v6_0_latency_watermark()
752 (wm->num_heads * cursor_line_pair_return_time); in dce_v6_0_latency_watermark()
758 if (wm->num_heads == 0) in dce_v6_0_latency_watermark()
772 b.full = dfixed_const(wm->num_heads); in dce_v6_0_latency_watermark()
807 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads)) in dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display()
827 (dce_v6_0_available_bandwidth(wm) / wm->num_heads)) in dce_v6_0_average_bandwidth_vs_available_bandwidth()
881 u32 lb_size, u32 num_heads) in dce_v6_0_program_watermarks() argument
895 if (amdgpu_crtc->base.enabled && num_heads && mode) { in dce_v6_0_program_watermarks()
931 wm_high.num_heads = num_heads; in dce_v6_0_program_watermarks()
958 wm_low.num_heads = num_heads; in dce_v6_0_program_watermarks()
1130 u32 num_heads = 0, lb_size; in dce_v6_0_bandwidth_update() local
1140 num_heads++; in dce_v6_0_bandwidth_update()
1146 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); in dce_v6_0_bandwidth_update()
1148 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); in dce_v6_0_bandwidth_update()